Datasheet
DD2.X
PowerPC 750CL Microprocessor
Preliminary
Bypass Register
The Bypass register is required by the IEEE 1149.1 standard. This is a single bit register that is used to
bypass the 750CL This feature allows a shorter system data scan string when scanning an entire system
board in which the 750CL boundary scan string is a part of a larger system data scan string.
Boundary Scan Register
The Boundary Scan register allows system board trace tests and access to the pins where physical access is
difficult. Basically, a latch is placed on inputs to capture data, and a latch is placed on outputs to force data.
Additional latches may be needed to configure bidirectional pins as either inputs or outputs and also to enable
or disable tri-state outputs. All these latches, or boundary scan cells, are serially connected to comprise the
boundary scan register.
Not all pins of the 750CL have an associated boundary scan cell. The five TAP pins and the dedicated test
pins do not have a boundary scan cell.
An industry-standard BSDL file is available for the 750CL with specific information on the boundary scan
register size and individual cell placement and function. This document can then be used to create card-level
connectivity tests between components.
5.11.3 Recommendations to Support System Debug
The TAP interface also allows functions such as observation and control of 750CL general-purpose registers,
cache contents, 60x bus cycles, and so forth, using the IBM RISCWatch debug tool. To simplify system
debug, the following system design recommendations are offered to allow use of RISCWatch and other diag-
nostic tools.
HRESET, SRESET, and TRST are signals used for RISCWatch to enable proper operation of the tool.
Logical AND gates should be placed between these signals and the IBM PowerPC 750CL RISC micropro-
cessor. See Table 5-4, Input/Output Usage, on page 51 and Figure 5-6, IBM RISCWatch JTAG to HRESET,
TRST, and SRESET Signal Connector, on page 55 for more information.
5.11.3.1 Processor Debug System Enablement when Implementing Precharge Selection
System designers who want to use a processor debug system attached to the 750CL IEEE 1149.1 test
access port (TAP) interface (such as the IBM RISCWatch debug system) should provide a method to assert
QACK after the transition of HRESET. Debug systems use a “soft stop” feature to stop the processor, allow
processor internal states to be read, and then a restart of the processor. A soft stop requires the system to be
in a quiescent state before the processor can be queried for internal state values. This is accomplished by the
assertion of a quiescent request (that is, QREQ is asserted) and subsequent acknowledgment (that is, QACK
is asserted). Systems that do not use the doze, nap, and sleep power management features, and do not
require the extended pre-charge feature, can drive the QACK pin with an inverted version of HRESET.
System Design Information
Page 66 of 70
Version 2.5
December 2, 2008
IBM [ IBM ]
