Datasheet
DD2.X
Preliminary
PowerPC 750CL Microprocessor
TRST is an optional pin, but it is required for 750CL to reset the TAP controller on a power-on reset (POR).
The 1149.1 standard requires a weak pullup only on the TRST pin, but in the 750CL, weak pullups are
provided to most TAP input pins such that the 750CL will function normally with the TAP pins unconnected.
However, it is recommended to tie the TDI and TMS input pins high and TRST low when they are not in use
for greater system reliability.
5.11.2 Supported IEEE 1149 JTAG Instructions and Data Registers
5.11.2.1 Instructions
750CL supports the three required JTAG instructions; Bypass, Sample/Preload, and Extest plus the optional
HIGHZ and CLAMP JTAG instructions. The 8-bit hexadecimal encoding for these instructions is shown in
Table 5-9. Hexadecimal encodings not included in the table are reserved for other functions.
JTAG instructions are scanned serially (least significant bit first) into an 8-bit TAP controller instruction
register through the TDI pin. Consult the IEEE 1149.1 standard for details regarding loading the JTAG
instructions using the TAP.
Table 5-9. Instruction Encodings
Instruction
EXTEST
SMPL_PLD
HIGHZ
Encoding
x‘00’
Description
JTAG extest instruction
JTAG sample/preload instruction
JTAG HIGHZ instruction
JTAG CLAMP instruction
JTAG bypass instruction
x‘C0’
x‘F0’
CLAMP
x‘F1’
BYPASS
x‘FF’
The instruction register output is forced to the Bypass instruction (all ones) if the TAP controller is in the
Test_Logic_Reset state or if TRST is active.
5.11.2.2 Data Registers
750CL supports the Bypass and Boundary Scan data registers. When selected with the corresponding JTAG
instruction (as shown in Table 5-10), the register is inserted between the TDI and TDO TAP pins and can be
scanned when the TAP controlled is in “Shift-DR” state to control or observe 750CL input and output states.
Consult the IEEE 1149.1 specification for details on manipulation of the data registers. An industry-standard
boundary scan design language (BSDL) file is available for 750CL with specific information on the boundary
scan latch size and organization. This document can be used to create card-level connectivity tests between
components.
Table 5-10. JTAG Instructions
Data Register
Instruction
Bypass
TAP State
Shift-DR
Shift-DR
Scan Clock
TCK
Data Register Length
Bypass register
1
Boundary scan register Sample/preload or extest
TCK
169
Version 2.5
System Design Information
Page 65 of 70
December 2, 2008
IBM [ IBM ]
