Datasheet
DD2.X
PowerPC 750CL Microprocessor
Preliminary
5.10.3 64-Bit or 32-Bit Data Bus Mode
The 750CL typically operates in 64-bit data bus mode. Mode setting is determined by the state of the mode
signal, TLBISYNC, at the transition of HRESET from its active to inactive state (low to high). If TLBISYNC is
high when HRESET transitions from active to inactive, 64-bit mode is selected. If TLBISYNC is low when
HRESET transitions from active to inactive, 32-bit mode is selected.
5.10.3.1 Precharge Duration Selection and Application
An extended precharge feature is available for the signals ABB, DBB, and ARTRY in situations where the
loading and net topology of these signals requires a longer precharge duration for the signals to attain a valid
level.
The bus signals, ABB, DBB, and ARTRY require a precharge to the inactive state (bus high) before going to
tristate. The precharge duration in standard precharge mode is approximately one half cycle, and should be
used for systems with point-to-point topologies. Extended precharge mode increases the precharge duration
to one cycle. This increase may be required for bus speeds approaching 200 MHz when bus loading is high.
QACK in a logical high state at the transition of HRESET from asserted to negated enables standard
precharge mode in the 750CL. QACK in a logical low state at the transition of HRESET from asserted to
negated enables extended precharge mode in the 750CL.
5.11 JTAG Test Access Port (TAP) Operation
750CL supports the IEEE 1149.1 standard, IEEE Standard Test Access Port and Boundary-Scan Architec-
ture. The standard defines a 5-pin interface that is used to perform functions such as continuity testing
between components on boards and system debug. Data is serially shifted into the processor through the TDI
pin and shifted out of the processor through the TDO pin. The scan operations can be divided into two cate-
gories: instruction scan and data scan operations. The operations or modes are selected using the TMS pin.
Finally, all scanning and mode selection is performed synchronously with respect to the clock pin, TCK.
This section details the IEEE 1149.1 operations supported by the 750CL processor and recommendations for
system design to support system debug using the TAP interface. For additional details, see the IEEE 1149.1
document.
5.11.1 Interface Pins
Table 5-8 provides a brief description of the five dedicated pins of the test access port (TAP). These pins do
not have an associated boundary scan cell.
Table 5-8. TAP Pins
Pin
TDI
Input/Output
Input
Weak Pullup
Mandatory TAP Pin
Function
Yes
No
Yes
Yes
Yes
Yes
No
Serial Scan input pin
Serial Scan output pin
TAP controller mode pin
Scan clock
TDO
TMS
TCK
TRST
Output
Input
Yes
No
Input
Input
Yes
TAP controller reset
System Design Information
Page 64 of 70
Version 2.5
December 2, 2008
IBM [ IBM ]
