Datasheet
DD2.X
PowerPC 750CL Microprocessor
Preliminary
Table 5-4. Input/Output Usage (Sheet 4 of 4)
Input/Output
with Internal
Pullup
Required
External
Resistor
750CL Signal
Name
Active
Level
Input/
Output
Level
Protect
Usage Group
Comments
Notes
Resistors
Internal
pullup enabled
TMS
High
Input
JTAG
5
Internal
pullup enabled
TRST
TS
Low
Low
Input
JTAG
2, 5
3, 4, 5
Pullup required to
OVDD
Input/Output Address Start
Keeper
1 K Ω
TSIZ[0:2]
TT[0:4]
VDD
High
High
—
Output
Transfer Attributes
Keeper
Keeper
1, 3, 4
1, 3, 4
Input/Output Transfer Attributes
—
Power Supply
WT
Low
Output
Transfer Attributes
Keeper
1, 3, 4
Notes:
1. Depends on the system design. The electrical characteristics of the 750CL do not add additional constraints to the system design,
so whatever is done with the net will depend on the system requirements.
2. HRESET, SRESET, and TRST are signals used for RISCWatch to enable proper operation of the debuggers. Logical AND gates
should be placed between these signals and the IBM PowerPC 750CL RISC Microprocessor (see Figure 5-6 on page 55 and
Section 5.11.3.1 on page 66).
3. The 750CL provides protection from meta-stability on inputs through the use of a “keeper” circuit on specific inputs (see
Section 5.10 on page 63 for a more detailed description).
4. If a system design requires a signal level to be maintained while not being actively driven, an external resistor or device must be
used (keepers assure no meta-stability of inputs but do not guarantee a level).
5. The 750CL does not require external pullups on address and data lines. Control lines must be treated individually.
6. Mode Select pins require the proper state at HRESET to configure the operating mode of the processor (see Table 5-7, Summary
of Mode Select, on page 63).
7. Use SYSCLK for single-ended operation: ground SYSCLK. For differential clock mode, a 50 Ω resistor to GND is required on both
SYSCLK and SYSCLK. See Reference Clock Selection on page 44. For single-ended operation, BVSEL must be continuously low.
For differential operation, BVSEL must be continuously pulled, driven, or connected to OVDD. See Table 4-1, Pinout Listing for the
FCPBGA Package, on page 41.
System Design Information
Page 54 of 70
Version 2.5
December 2, 2008
IBM [ IBM ]
