Datasheet
DD2.X
Preliminary
PowerPC 750CL Microprocessor
5.7.1 Input/Output Usage
Table 5-4 provides details on the input/output usage of the 750CL signals. The “Usage Group” column refers
to the general functional category of the signal.
In the 750CL, certain input/output signals have pullups and pulldowns, which may or may not be enabled. In
Table 5-4, the “Input/Output with Internal Pullup Resistors” column defines which signals have these pullups
or pulldowns and their active or inactive state. The “Level Protect” column defines which signals have the
designated function added to their input/output cell. For more about level protection, see Section 5.10.1 on
page 63.
Table 5-4. Input/Output Usage (Sheet 1 of 4)
Input/Output
Required
750CL Signal
Name
Active
Level
Input/
Output
with Internal
Pullup
Level
Usage Group
External
Resistor
Comments
Notes
Protect
Resistors
A[0:31]
AACK
High
Input/Output Address Bus
Keeper
1, 3, 4
Must be actively
driven
Low
Input
Address Termination
Keeper
Keeper
3, 4, 5
3, 4, 5
Pullup required to
OVDD
ABB
Low
—
Input/Output
—
—
1 K Ω
1 K Ω
AGND
ARTRY
AVDD
BG
Power Supply
Pullup required to
OVDD
Low
—
Input/Output Address Termination
Keeper
3, 4, 5
—
PLL Power Supply
Address Arbitration
Active driver or
pulldown
Low
Input
Keeper
Keeper
3, 4, 5
3, 4, 5
Chip actively
drives
BR
Low
Output
Address Arbitration
Internal pullup
enabled
Pullup/pulldown,
as required
BVSEL
CI
N/A
Low
Low
Input
Mode Select
1 K Ω
5
Output
Input
Transfer Attributes
Interrupt/Resets
Keeper
Keeper
1, 3, 4
3, 4, 5
Must be actively
driven
CKSTP_IN
Notes:
1. Depends on the system design. The electrical characteristics of the 750CL do not add additional constraints to the system design,
so whatever is done with the net will depend on the system requirements.
2. HRESET, SRESET, and TRST are signals used for RISCWatch to enable proper operation of the debuggers. Logical AND gates
should be placed between these signals and the IBM PowerPC 750CL RISC Microprocessor (see Figure 5-6 on page 55 and
Section 5.11.3.1 on page 66).
3. The 750CL provides protection from meta-stability on inputs through the use of a “keeper” circuit on specific inputs (see
Section 5.10 on page 63 for a more detailed description).
4. If a system design requires a signal level to be maintained while not being actively driven, an external resistor or device must be
used (keepers assure no meta-stability of inputs but do not guarantee a level).
5. The 750CL does not require external pullups on address and data lines. Control lines must be treated individually.
6. Mode Select pins require the proper state at HRESET to configure the operating mode of the processor (see Table 5-7, Summary
of Mode Select, on page 63).
7. Use SYSCLK for single-ended operation: ground SYSCLK. For differential clock mode, a 50 Ω resistor to GND is required on both
SYSCLK and SYSCLK. See Reference Clock Selection on page 44. For single-ended operation, BVSEL must be continuously low.
For differential operation, BVSEL must be continuously pulled, driven, or connected to OVDD. See Table 4-1, Pinout Listing for the
FCPBGA Package, on page 41.
Version 2.5
System Design Information
Page 51 of 70
December 2, 2008
IBM [ IBM ]
