Datasheet
DD2.X
Preliminary
PowerPC 750CL Microprocessor
4.4 Pinout Listings
Table 4-1 contains the pinout listing for the 750CL FCPBGA package.
Table 4-1. Pinout Listing for the FCPBGA Package (Sheet 1 of 3)
Signal Name
Pin Number
Active
High
Input/Output
Input/Output
Notes
E20, E19, D20, C20, D19, C19, A20, E16, B20, E17,
B18, A18, A17, A19, A16, B16, B10, B9, A9, B7, A7,
D8, A5, B6, D7, D5, B5, B4, A4, A3, B3, E5.
A[0:31]
AACK
ABB
A8
Low
Low
—
Input
Input/Output
—
Y6
AGND
ARTRY
AVDD
BG
Y14
W7
Y15
W4
Y3
Low
—
Input/Output
—
Low
Low
—
Input
BR
Output
Input
BVSEL
W9
Y12
T4
3
CKSTP_OUT
CI
Low
Low
Low
Output
Output
Input
CKSTP_IN
CLK_OUT
DBB
Y10
T5
Output
Output
Input
U7
Low
Low
Low
DBG
Y5
DBWO
A6
Input
W18, T17, Y20, Y19, W20, V19, U19, T16, T19, U20,
V20, R19, N17, P17, R20, P20, N20, P19, M20, L20,
M19, L19, K20, J19, K19, G20, H20, H17, H19, F19,
G17, F20
DH[0:31]
DL[0:31]
High
High
Input/Output
Input/Output
A2, A1, C2, E4, C1, E2, D2, E1, D1, F1, G2, F2, H2,
H4, G1, K2, J2, K1, J1, L2, M2, L1, N2, N4, N1, P1, P4,
P2, R2, R1, U2, T1
DRTRY
EFUSE
GBL
W3
Y16
W1
Low
N/A
Low
Input
Input
8
Input/Output
Notes:
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. OVDD inputs supply power to the input/output drivers and VDD inputs supply power to the processor core.
3. BVSEL low selects single-ended clock input on SYSCLK. BVSEL high selects differential clock input on SYSCLK and SYSCLK.
4. TCK must be tied high or low for normal machine operation.
5. No ball is installed in this location.
6. SYSCLK is the active low clock input used with SYSCLK in differential mode. In single-ended mode, SYSCLK is used as the clock
input, and SYSCLK is grounded.
7. Must be connected to OVDD during normal operation.
8. Must be connected to GND during normal operation.
9. Kelvin VDD and GND for voltage regulator sensing.
10. On DD1.x, this signal must be pulled up to OVDD for normal operation. On DD2.x, this signal selects the I/O operating voltage such
that a pulldown to GND selects 1.8 V and a pull up to OVDD selects 1.15 V.
Version 2.5
Dimensions and Signal Assignments
Page 41 of 70
December 2, 2008
IBM [ IBM ]
