Datasheet
DD2.X
Preliminary
PowerPC 750CL Microprocessor
Table 5-1. 750CL Microprocessor PLL Configuration (Sheet 2 of 2)
PLL_CFG [0:4]
Processor to Bus Frequency Ratio
(PTBFR)
Binary
10010
10011
10100
Decimal
18
9×
19
9.5×
10×
20
Notes:
1. The SYSCLK frequency equals the core frequency divided by the processor-to-bus frequency ratio (PTBFR).
5.3 PLL Power Supply Filtering
The 750CL microprocessor has an AV signal that provides power to the clock generation PLL.
DD
To ensure stability of the internal clock, the power supplied to the AV input signals should be filtered using
DD
a circuit similar to the one shown in Figure 5-1. The circuit should be placed as close as possible to the AV
DD
pin to ensure it filters out as much noise as possible.
Figure 5-1. PLL Power Supply Filter Circuit
Discrete Resistor
Ferrite Bead1
2
Ω
AVDDPin
C1
C2
AVDD
AGND Pin1
Item
Resistor
C1
Description/Value
2 Ω
0.1 μF Ceramic
C2
10.0 μF Ceramic
Ferrite Bead
30 Ω (typical) - Murata BLM21P300S or similar
Notes:
1. Connected to ground without a filter.
Version 2.5
December 2, 2008
System Design Information
Page 45 of 70
IBM [ IBM ]
