Datasheet
DD2.X
PowerPC 750CL Microprocessor
Preliminary
Table 3-7. 60x Bus Input AC Timing Specifications
See Table 3-2 on page 22 for operating conditions.1, 4, 5
Part Numbers
≤
Part Numbers
>
733 MHz
Figure 3-4 and
3-5
Characteristic
Timing
Unit
Notes
7
733 MHz
Reference
Min.
1.0
Max.
Min.
1.0
Max.
Slew Rate
Notes:
Reference input slew rate
—
—
V/ns
1. Input specifications are measured from the midpoint voltage (VM) of the signal in question to the VM of the rising edge of the input
SYSCLK. Timings are measured at the pin (see Figure 3-4 on page 29). Timing values apply while OVDD = 1.5 V nominal and
OVDD = 1.8 V nominal.
2. tSYSCLK is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by
the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
3. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255
bus clocks after the PLL relock time during the power-on reset sequence.
4. All values are guaranteed by design, and are not tested.
5. See Section 3.5.1 on page 28 and Figure 3-3 on page 29 for input setup timing definitions.
6. Input reference signal levels used to establish the timings defined in this table.
7. Input slew rate refers to the slew rate between VIH-AC and VIL-AC timing reference levels.
8. INT, SMI, MCP, and CHKSTP_IN must remain asserted until recognized by the processor.
3.5.1 Input Setup Timing
The information in this subsection is provided to clarify the criteria used to establish the timings in Table 3-7.
The 60x Bus Input AC Timing Specifications shown in Table 3-7 are not altered by this clarification. The valid
input signal levels remain V and V .
IH
IL
The input setup times shown as 10a in Table 3-7 specify the required time from the input signal crossing V
M
to the rising edge of SYSCLK crossing V .
M
For the timings in Table 3-7 to be valid, the falling edge of the input signal shown in Table 3-7 is assumed to
transition through V and cross V at the slew rate specified in Table 3-7. Input signals that do not reach
M
IL-AC
the V
boundary, or that slew from V to V
more slowly than specified, will result in longer input setup
IL-AC
M
IL-AC
times.
In the same way, on the rising edge, the input signal must continue past V and cross the V
boundary
IH-AC
M
within the specified minimum slew rate. Input signals that do not reach the V
rate specified will result in longer input setup times.
boundary within the slew
IH-AC
Figure 3-4 on page 29 provides the input timing diagram for the 750CL.
Electrical and Thermal Characteristics
Page 28 of 70
Version 2.5
December 2, 2008
IBM [ IBM ]
