Datasheet
DD2.X
PowerPC 750CL Microprocessor
Preliminary
Figure 3-5 provides the mode select input timing diagram for the 750CL.
Figure 3-5. Mode Select Input Timing Diagram
V
IH
HRESET
10c
10c
11c
11c
Mode Pins
3.5.2 Following HRESET Deassertion
Previous PowerPC processors begin arbitrating for the bus shortly after the deassertion of HRESET. In
contrast, the 750CL waits about 25000 bus clock cycles following the deassertion of HRESET to begin arbi-
trating for the bus. Until that time, the processor is effectively held in reset. The bus logic and other bus
agents should not assume that the 750CL is monitoring the bus until the 750CL first asserts BR (or TS, if the
bus is parked on the processor).
Electrical and Thermal Characteristics
Page 30 of 70
Version 2.5
December 2, 2008
IBM [ IBM ]
