Datasheet
DD2.X
Preliminary
PowerPC 750CL Microprocessor
Figure 3-2. Linear Sweep Modulation Profile
0%
Down spread
frequency
change
-1%
0 μs
33.3 μs
Time Increases
3.5 60x Bus Input AC Specifications
Table 3-7 provides the 60x bus AC timing specifications defined in Figure 3-4 and Figure 3-5 on page 30.
Table 3-7. 60x Bus Input AC Timing Specifications
See Table 3-2 on page 22 for operating conditions.1, 4, 5
Part Numbers
≤
Part Numbers
>
733 MHz
Figure 3-4 and
3-5
Timing
Reference
Characteristic
Unit
ns
Notes
733 MHz
Min.
1.6
Max.
Min.
1.15
Max.
10a
10c
11a
11c
Input setup: SYSCLK to all inputs valid
—
—
—
—
8
2
Mode select input setup to HRESET, TLBISYNC,
QACK, and DRTRY
SYSCLK
cycles
8
—
0
8
—
0
Input hold: SYSCLK to inputs invalid
600
—
350
—
ps
HRESET to mode select input hold TLBISYNC,
QACK, and DRTRY
SYSCLK
cycles
3
6
VM
VIL-AC
Measurement reference voltage for inputs
—
—
0.2
—
—
0.2
—
AC timing reference levels
V
VIH-AC
OVDD-0.2
OVDD-0.2
Notes:
1. Input specifications are measured from the midpoint voltage (VM) of the signal in question to the VM of the rising edge of the input
SYSCLK. Timings are measured at the pin (see Figure 3-4 on page 29). Timing values apply while OVDD = 1.5 V nominal and
OVDD = 1.8 V nominal.
2. tSYSCLK is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by
the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
3. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255
bus clocks after the PLL relock time during the power-on reset sequence.
4. All values are guaranteed by design, and are not tested.
5. See Section 3.5.1 on page 28 and Figure 3-3 on page 29 for input setup timing definitions.
6. Input reference signal levels used to establish the timings defined in this table.
7. Input slew rate refers to the slew rate between VIH-AC and VIL-AC timing reference levels.
8. INT, SMI, MCP, and CHKSTP_IN must remain asserted until recognized by the processor.
Version 2.5
Electrical and Thermal Characteristics
Page 27 of 70
December 2, 2008
IBM [ IBM ]
