IBMN625404GT3B
IBMN625804GT3B
Preliminary
256Mb Double Data Rate Synchronous DRAM
Block Diagram (32Mb x 8)
QFC
generator
CKE
CK
QFC
(Optional)
DRVR
CK
CS
WE
CAS
RAS
Bank3
Bank2
Bank1
CK, CK
DLL
Mode
Registers
13
8192
Bank0
Memory
Array
Data
1
13
15
(8192 x 512 x 16)
8
8
8
16
Sense Amplifiers
DQS
Generator
DQ0-DQ7,
DM
COL0
Mask
DQS
Input
Register
1
I/O Gating
DM Mask Logic
16
2
DQS
1
A0-A12,
BA0, BA1
Write
15
1
8
FIFO
1
1
&
16
2
16
2
512
Drivers
(x16)
8
8
8
8
clk
clk
Column
Decoder
in
out
Data
9
COL0
CK,
CK
Column-Address
Counter/Latch
10
COL0
1
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
29L0011.E36997B
1/01
Page 7 of 79
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