Preliminary
IBMN625404GT3B
IBMN625804GT3B
256Mb Double Data Rate Synchronous DRAM
DDR SDRAM Device Labeling Guide
P/N code: aaabbccddefggh - jjj
Meaning
Digit
aaa
bb
cc
dd
Manufacturer
Product family/quality
designator
Density & Addressing
Data Width
Number of logical banks
and QFC\ support
Power (all devices sup-
port self refresh mode)
All Devices IBM
All Devices 06 = Industry Standard premium DDR SDRAM
All Devices 25 = 256Mb, 13 row (4 bank devices only)
Planar
Devices
All Devices
40 = x4
80 = x8
4 = 4 logical banks, does not support QFC\ function
5 = 4 logical banks, includes QFC\ function
Applies to
Definition
e
f
All Devices G = Standard Power, SSTL_2, V
dd
=V
ddq
=2.5V
1st Digit:
T = TSOP
2nd Digit:
3 = 400 mil package width
gg
Package Type
All Devices
h
Die Revision Code
Part Speed Designator:
This is specified at the
maximum clock fre-
quency of the device.
However, the same
device will support
smaller CAS latencies
for lower frequencies.
All Devices B = 1st shrink
1st and 2nd Digit: (2nd digit is dropped if representing x.0 ns)
7 = Intended for 143MHz @CL=2.5
75= Intended for 133MHz @ CL=2.5
8 = Intended for 125MHz @ CL=2.5
3rd Digit (represents CL/t
RCD
/t
RP
for the specific clock cycle
defined by the 1st and 2nd digits above):
N: CL=2.5, t
RCD
= 3, t
RP
=3
jjj
All Devices
29L0011.E36997B
1/01
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 79
IBM [ IBM ]
