IBMN625404GT3B
IBMN625804GT3B
256Mb Double Data Rate Synchronous DRAM
Preliminary
Block Diagram (64Mb x 4)
QFC
generator
QFC
(Optional)
CKE
CK
DRVR
CK
CS
WE
CAS
RAS
Bank3
Bank2
Bank1
CK, CK
DLL
Mode
13
Registers
8192
Bank0
Memory
Array
Data
15
13
(8192 x 1024 x 8)
4
4
4
8
Sense Amplifiers
1
DQS
Generator
DQ0-DQ3,
DM
COL0
Mask
DQS
Input
Register
1
I/O Gating
DM Mask Logic
8
2
DQS
1
1
A0-A12,
BA0, BA1
Write
15
1
FIFO
1
&
8
2
8
1024
(x8)
2
Drivers
4
4
4
4
4
clk
clk
Column
Decoder
in
out
Data
10
1
COL0
CK,
CK
Column-Address
Counter/Latch
11
COL0
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
29L0011.E36997B
1/01
Page 6 of 79