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IBMN325404CT3B-75H 参数 Datasheet PDF下载

IBMN325404CT3B-75H图片预览
型号: IBMN325404CT3B-75H
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 64MX4, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 66 页 / 1699 K
品牌: IBM [ IBM ]
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IBMN325164CT3  
IBMN325804CT3  
IBMN325404CT3  
Preliminary  
256Mb Synchronous DRAM - Die Revision B  
Automatic Refresh Command (CAS before RAS Refresh)  
When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters  
the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of  
the Precharge time (t ) before the Auto Refresh Command (CBR) can be applied. For a stacked device,  
RP  
both decks may be refreshed at the same time using Automatic Refresh Mode. An address counter, internal  
to the device provides the address during the refresh cycle. No control of the external address pins is  
required once this cycle has started.  
When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay  
between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh  
Command must be greater than or equal to the Refresh cycle time (t  
).  
RFC  
Self Refresh Command  
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command  
is defined by having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks  
must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held  
low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the  
external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Oper-  
ation to save power. The user may halt the external clock while the device is in Self Refresh mode, however,  
the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the  
device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the  
device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the  
Refresh cycle time (t  
) plus the Self Refresh exit time (t  
). When using Self Refresh, both decks of a  
RFC  
SREX  
stacked device may be refreshed at the same time.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
06K0608.F39375A  
10/00  
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