IBMN325164CT3
IBMN325804CT3
IBMN325404CT3
Preliminary
256Mb Synchronous DRAM - Die Revision B
Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it
can be interrupted by a Read or Write Command to a different bank. If the command is issued before auto-
precharge begins then the precharge function will begin with the new command. The bank being auto-pre-
charged may be reactivated after the delay t
.
RP
Burst Read with Auto-Precharge Interrupted by Read
(Burst Length = 4, CAS Latency = 2, 3)
T5 T6 T7 T8
T0
T1
T2
T3
T4
CK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ B
DOUT A
COMMAND
Auto-Precharge
t
‡
RP
CAS latency = 2
*
tCK2, DQs
DOUT A
t
DOUT B
DOUT B
DOUT B
DOUT B
3
0
1
0
1
2
‡
RP
CAS latency = 3
*
tCK3, DQs
DOUT A
DOUT A
DOUT B
DOUT B
DOUT B
DOUT B
3
0
1
0
1
2
Bank can be reactivated at completion of t
.
RP
*
‡ t is a function of clock cycle time and speed sort.
RP
See the Clock Frequency and Latency table.
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ
contention.
Burst Read with Auto-Precharge Interrupted by Write
(Burst Length = 8, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRITE B
COMMAND
Auto-Precharge
t
‡
RP
*
CAS latency = 2
t
CK2, DQs
DOUT A
DIN B
0
DIN B
DIN B
DIN B
DIN B
4
0
1
2
3
DQM
Bank can be reactivated at completion of t
.
RP
*
‡ t is a function of clock cycle time and speed sort..
RP
See the Clock Frequency and Latency table.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K0608.F39375A
10/00
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