Preliminary
IBMB3N32644HCB
IBMB3N32734HCB
32M x 64/72 One-Bank Unbuffered SDRAM Module
(Part 2 of 2)
SPD Entry Value
Undefined
1.2
Checksum Data
IBM
MM
16M x 64,
-75A
16M x 72,
-75A
ASCII ‘B3N32644HCB-75AT’
ASCII ‘B3N32734HCB-75AT’
‘B’ plus ASCII blank
Year/Week Code
Serial Number
Undefined
100 MHz
CK0, CK2, CL2, CL3
concurrent AP
Undefined
Serial PD Data Entry (Hexa-
decimal)
00
12
cc
A400000000000000
mm
42334E31363634344A43
422D373541542020
42334E31363733344A43
422D373541542020
4220
yyww
ssssssss
00
64
A7
00
8
8
7
2
Notes
Serial Presence Detect
Byte #
42 - 61
62
63
64 - 71
72
Reserved
SPD Revision
Checksum for bytes 0 - 62
Manufacturers’ JEDEC ID Code
Module Manufacturing Location
Description
73 - 90
Module Part Number
91 - 92
93 - 94
95 - 98
Module Revision Code
Module Manufacturing Date
Module Serial Number
99 - 125 Reserved
126
127
Module Supports this Clock Frequency
Attributes for Clock Frequency defined in byte 126
128 - 255 Open for Customer Use
1.
2.
3.
4.
5.
6.
7.
8.
See the AC output load circuit in the AC Characteristics section below
cc = Checksum Data byte, 00-FF (Hex)
“MM” = Alphanumeric revision code, A-Z, 0-9
mm= ASCII coded revision code byte “MM”
yy = Binary coded decimal year code, 00-99 (Decimal) 00-63 (Hex)
ww = Binary coded decimal week code, 01-52 (Decimal) 01-34 (Hex)
ss = Serial number data byte, 00-FF (Hex)
For PC-100 applications only.
06K3671.H01574
11/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 18
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