IBMB3N32644HCB
IBMB3N32734HCB
32M x 64/72 One-Bank Unbuffered SDRAM Module
Preliminary
Serial Presence Detect (Part 1 of 2)
Serial PD Data Entry (Hexa-
Byte #
Description
SPD Entry Value
Notes
decimal)
0
1
2
3
4
5
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
128
80
256
08
SDRAM
04
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Banks
13
0D
0A
01
10
1
16M x 64
16M x 72
x64
4000
4800
01
6 - 7
Data Width of Assembly
x72
8
9
Voltage Interface Level of this Assembly
SDRAM Device Cycle Time at CL=3
LVTTL
7.5ns
75
1
10
SDRAM Device Access Time from Clock at CL=3
5.4ns
54
16M x 64
16 M x 72
Non-Parity
00
11
DIMM Configuration Type
ECC
02
12
13
Refresh Rate/Type
SR/1x(15.625us)
80
Primary SDRAM Device Width
x8
08
16M x 64
16M x 72
N/A
00
14
Error Checking SDRAM Device Width
x8
08
15
16
17
18
19
20
21
SDRAM Device Attr: Min Clk Delay, Random Col Access
SDRAM Device Attributes: Burst Lengths Supported
SDRAM Device Attributes: Number of Device Banks
SDRAM Device Attributes: CAS Latencies Supported
SDRAM Device Attributes: CS Latency
1 Clock
01
1,2,4,8
0F
4
04
2, 3
06
0
0
01
SDRAM Device Attributes: WE Latency
01
SDRAM Module Attributes
Unbuffered
00
Wr-1/Rd Burst, Precharge All,
Auto-Precharge, VDD +/- 10%
22
SDRAM Device Attributes: General
0E
23
24
25
26
27
28
29
Minimum Clock Cycle at CL=2
15.0ns
9.0ns
N/A
F0
90
00
00
14
0F
14
Maximum Data Access Time (tAC) from Clock at CL=2
1
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time (tAC) from Clock at CL=1
N/A
Minimum Row Precharge Time (tRP
Minimum Row Active to Row Active delay (tRRD
Minimum RAS to CAS delay (tRCD
)
20ns
15ns
20ns
)
)
Minimum RAS Pulse width (tRAS
)
30
31
32
33
34
35
45ns
256MB
1.5ns
2D
40
15
08
15
08
00
43
Module Bank Density
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Data Input Setup Time Before Clock
0.8ns
1.5ns
Data Input Hold Time After Clock
0.8ns
36 - 40 Reserved for VCSDRAM
Minimum Bank Cycle Time (tRC
Undefined
67ns
)
41
1. See the AC output load circuit in the AC Characteristics section below
2. cc = Checksum Data byte, 00-FF (Hex)
3. “MM” = Alphanumeric revision code, A-Z, 0-9
4. mm= ASCII coded revision code byte “MM”
5. yy = Binary coded decimal year code, 00-99 (Decimal) 00-63 (Hex)
6. ww = Binary coded decimal week code, 01-52 (Decimal) 01-34 (Hex)
7. ss = Serial number data byte, 00-FF (Hex)
8. For PC-100 applications only.
06K3671.H01574
11/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 18
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