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IBMB3N32734HCB-75AT 参数 Datasheet PDF下载

IBMB3N32734HCB-75AT图片预览
型号: IBMB3N32734HCB-75AT
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM Module, 32MX72, 5.4ns, CMOS, DIMM-168]
分类和应用: 时钟动态存储器内存集成电路
文件页数/大小: 18 页 / 314 K
品牌: IBM [ IBM ]
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IBMB3N32644HCB  
IBMB3N32734HCB  
32M x 64/72 One-Bank Unbuffered SDRAM Module  
Preliminary  
Operating, Standby, and Refresh Currents (TA= 0 to +70°C, VDD= 3.3V ± 0.3V)  
Organization  
Parameter  
Symbol  
Test Condition  
Units  
Notes  
1, 2  
x64  
960  
x72  
1 Bank operation  
= t (min), t = min  
t
RC  
RC  
CK  
Operating Current  
I
1080  
mA  
CC1  
Active-Precharge command cycling  
without Burst operation  
CKE0 V (max), t = min,  
IL  
CK  
I
16  
16  
18  
18  
mA  
mA  
mA  
mA  
mA  
CC2P  
S0, S2 =V (min)  
IH  
Precharge Standby Current in Power  
Down Mode  
CKE0 V (max), t = Infinity,  
IL  
CK  
I
CC2PS  
S0, S2 =V (min)  
IH  
CKE0 V (min), t = min,  
IH  
CK  
I
240  
64  
270  
72  
3
4
3
CC2N  
S0, S2 =V (min)  
IH  
Precharge Standby Current in Non-  
Power Down Mode  
CKE0 V (min), t = Infinity,  
IH  
CK  
I
CC2NS  
S0, S2 =V (min)  
IH  
CKE0 V (min), t = min,  
IH  
CK  
I
480  
540  
CC3N  
S0, S2 =V (min)  
IH  
No Operating Current  
(Active state: 4 bank)  
CKE0 V (max), t = min,  
IL  
CK  
I
S0, S2 =V (min)  
48  
54  
mA  
5
CC3P  
IH  
(Power Down Mode)  
t
= min,  
CK  
Read/write command cycling,  
multiple banks active,  
gapless data, BL = 4  
Burst Operating Current  
I
960  
1080  
1575  
mA  
mA  
2, 6  
CC4  
t
= min, t = t (min),  
RC RC  
CK  
Auto (CBR) Refresh Current  
I
I
1400  
CC5  
CBR command cycling  
Self Refresh Current  
CKE0 0.2V  
24  
30  
27  
30  
mA  
CC6  
Serial PD Device Standby Current  
I
V
= GND or V  
DD  
µA  
7
8
SB  
IN  
Serial PD Device Active Power Sup-  
ply Current  
I
SCL Clock Frequency = 100KHz  
1
1
mA  
CCA  
1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t and t  
.
RC  
CK  
Input signals are changed up to three times during t (min).  
RC  
2. The specified values are obtained with the output open.  
3. Input signals are changed once during three clock cycles.  
4. Input signals are stable.  
5. Active standby current will be higher if Clock Suspend is entered during a Burst Read cycle (add 1mA per DQ).  
6. Input signals are changed once during t  
.
ck(min)  
7. V = 3.3V  
DD  
8. Input pulse levels V x 0.1 to V x 0.9, input rise and fall times 10ns, input and output timing levels V x 0.5, output load 1 TTL  
DD  
DD  
DD  
gate and CL=100pf.  
06K3671.H01574  
11/00  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
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