IBM39STB032xx
IBM39STB034xx
Preliminary
STB032xx and STB034xx Digital Set-Top Box Integrated Controllers
I/O Timing Diagrams
AC Specification
Note 1. Clock timing and switching characters are specified in accordance with operating conditions in
Recommended Operating Conditions on page 35. AC specifications assume a 30 pF output load. All input
slow rates must be 5 ns or less, unless otherwise specified (rise and fall times measured between 0.8 V
and 2.0 V). Also, all input clocks must have a 40–60% duty cycle, unless otherwise specified.
Note 2. The internal SysClk is shown in the diagrams to indicate the relationship of the number of cycles
between various signal edges on the timing diagram.
Note 3. Where multiple interfaces share the same timing diagram, the signals names are listed using an
‘n’ to indicate that the timings apply to both interfaces. For example, the SD0 and SD1 interface signal
names in the SDRAM interface timing diagram are listed as ‘SDn’.
G_SysClk Timing
TCF
TCL
TCR
TCH
2.0 V
1.5 V
0.8 V
TC
SysClk Timing Values
Symbol
Parameter
Min
Max
Units
MHz
ns
F
SysClk clock input frequency
(Nominal 27)
C
1
T
T
Clock edge stability
0.15
CS
CH
Clock input high time
Clock input low time
15
15
ns
T
ns
CL
2
T
Clock input rise time
0.6
0.6
ns
CR
2
T
Clock input fall time
ns
CF
Note 1. Cycle-to-cycle jitter allowed between any two edges.
Note 2. Rise and fall times measured between 0.8 V and 2.0 V.
STB03_sds_041800.fm.01
April 18, 2000
Electrical Information
Page 37 of 55
IBM [ IBM ]
