IBM39STB032xx
IBM39STB034xx
STB032xx and STB034xx Digital Set-Top Box Integrated Controllers
Preliminary
SRAM Interface Timing Values (Continued)
Symbol
Parameter
Min
3
Max
15
Units
ns
T
T
T
Data input hold time
Data output valid time
Data output hold time
13
14
16
ns
3
ns
SDRAM Interface Timing Diagram
t1
SDn_CLK
Output
SDn_DATA,
Controls
Output
Input
VALID
t2
t3
SDn_DATA
t4
t5
SDRAM Interface Timing Values
Symbol
Parameter
Min
Max
Units
ns
T
T
T
T
T
SD_clk clock period (at SYSCLK = 54 MHz)
Output valid time
9.25
1
2
3
4
5
7.25
ns
Output hold time
1
1
ns
Input setup time
ns
Input hold time
2.5
ns
Notes:
T
T
T
T
= (2, 3, or 4) x t1 – controlled by SDRAMC Bank Register bits [21:22]
RCD
= (5 or 6) x t1 – controlled by SDRAMC System Register bit 4
RAS
= (2, 3, or 4) x t1 – controlled by SDRAMC Bank Register bits [25:26]
= (7, 8, 9, or 10) x t1 – controlled by SDRAMC Bank Register bits [30:31]
RP
RC
Electrical Information
Page 40 of 55
STB03_sds_041800.fm.01
April 18, 2000
IBM [ IBM ]
