IBM PowerPRS Q-64G
Packet Routing Switch
Preliminary
The ingress side of the PowerPRS Q-64G receives one subport output queue grant per port (0 to 31), per
subport (0 to 3), and per priority (0 to 3) and one subport multicast grant per port (0 to 31) and per priority
(0 to 3). Although the PowerPRS Q-64G broadcasts all the subport output queue grants via egress packets, it
broadcasts only two subport multicast grants per priority (one for ports 0 to 15 and one for ports 16 to 31).
The subport multicast grants broadcast to ports 0 to 15 and to ports 16 to 31 are the logical AND of the
ingress flow control information for their respective port ranges. Consequently, a subport multicast grant for a
port range and priority is issued only if the output queue grant status for all 16 ports in the range is active.
The internal subport grant table is refreshed only once per packet cycle. This guarantees that all the attached
devices receive the same flow control information.
3.7 Flow Control Information Summary
The PowerPRS Q-64G stores the current status of the various flow control grants in internal tables. Each
grant requires one bit of table capacity. Table 3-25 summarizes the types of flow control grants, the compo-
nents for which each type of grant is issued, and the resulting number of bits required to store the grant status
in the table.
Table 3-25. Flow Control Information Summary
Components for Which Grants are Issued
Total Number of
Table Bits Required
Flow Control Grant Type
Subswitch Elements
A/B and C/D
Ports
Subports
Priorities
0 to 3
Output queue grants
Memory grants
0 to 31
256
2
A/B and C/D
Multicast grants
A, B, C, and D
0 to 3
0 to 3
0 to 3
0 to 3
16
Send grants
0 to 31
0 to 31
0 to 31
128
512
128
Subport output queue grants
Subport multicast grants
0 to 3
3.8 Packet Reception
Packet reception on a particular input port is not synchronized with packet reception on the other input ports.
When a packet arrives at an input port, the input controller analyzes the packet header and extracts various
fields. If the header parity is incorrect, the entire packet is discarded. This error is reported via the header
parity error bit in the Status Register (page 120), and the affected port is identified in the Header Parity Error
Register (page 132). An interrupt is generated unless the error is masked with the header parity error bit in
the Interrupt Mask Register (page 122). If the header parity is correct, the packet type is analyzed and the
flow control information is extracted. Further processing depends on the packet type and is discussed in
Sections 3.8.1 and 3.8.2.
In speed expansion configurations, the input controller on the master device conducts the packet header
analysis and extraction, and then forwards the packet control information to the input controllers on the slave
devices.
Note: A multicast packet is routed to only one subswitch element and stored only once in the shared mem-
ory; however, its shared memory address is enqueued in each output queue designated by the destination
bitmap. In the 256-Gbps configuration, all destination output ports must be within the 0 to 7 port range or the
Functional Description
Page 54 of 199
prsq-64g.01.fm
December 20, 2001
IBM [ IBM ]
