Datasheet
PowerPC 970FX RISC Microprocessor
Figure 3-4. Typical Implementation for a Single-Ended Line
OV
DD
OV
DD
Z
d
TR0
Z0
R
TR0
Z
d
L
SSB
V
REF-SSB
Table 3-10. Processor Interconnect SSB Driver Specifications
Symbol
Description
Minimum
Typical
Maximum
Units
Notes
V
DC High output level at dc
DC Low output level at dc
0.87 OV
0.13 OV
133
mV
mV
ps
ps
Ω
OH
DD
DD
V
OL
T
Signal driver rise time
70
81
15
30
171
162
25
20% to 80% of swing
20% to 80% of swing
Low-Ω mode
DR
T
Signal driver fall time
155
DF
Z
Signal driver output impedance
Signal driver output impedance
20
D
D
Z
40
50
Ω
High-Ω mode
3.5.1.3 Module-to-Module Interconnect Characteristics
All traces are to be routed as striplines or microstrip. The tolerance on trace impedance is 10%. Care must be
taken when mixing transmission line styles to manage propagation delay differences. The clock delay should
be longer than the longest data delay for bus speeds at or higher than 1.1 Gbps or on lines longer than
13 cm.
Table 3-11. Processor Interconnect SSB Printed Circuit Board Trace Specifications
Symbol
Description
Trace length
Minimum
Typical
Maximum
18
Units
cm
cm
Ω
Notes
For transfer speeds of 1.5 Gps.
For transfer speeds of 1.0 Gps.
L
SSB
22.5
55
Z
Trace impedance
45
50
0
Printed circuit board
data trace skew
S
150
ps
DPCB
Version 2.5
Electrical and Thermal Characteristics
Page 31 of 78
March 26, 2007
IBM [ IBM ]
