Datasheet
PowerPC 970FX RISC Microprocessor
3.5 Processor Interconnect Specifications
3.5.1 Electrical and Physical Specifications
3.5.1.1 Source Synchronous Bus
Figure 3-3 provides a representative block diagram of a source synchronous bus (SSB) for a
PowerPC 970FX RISC Microprocessor processor interconnect implementation. Each SSB consists of three
major subsections: the drive side, the module-to-module interconnect, and the receive side. First, data is
either balance-coding-method encoded or checksummed, then clock-phase multiplexed, and finally launched
from the drive side onto the module interconnect. The receive side includes far-end termination and circuitry
to demultiplex, deskew data, align clocks, and synchronize the received data.
Figure 3-3. Block Diagram of an SSB for a Processor Interconnect Implementation
TERM
D
R
TERM
D
R
Clock
Distribution
Clock
Source
D
R
TERM
Drive Side
Interconnect
Receive Side
3.5.1.2 Drive Side Characteristics
Figure 3-4 shows a typical implementation for a single-ended line. The drivers are of the push-pull type with a
nominal impedance (R0 of 20 Ω) that overdrives the line impedance. The nominal swing at the receiver,
terminated with resistance (TR0 of 110 Ω) to each rail, is 13% OVDD to 87% OVDD. R0 is 20 Ω when the
signal driver is in the low output impedance mode. The 20 Ω setting is suitable for all bus speeds. The
PowerPC 970FX has a 40 Ω nominal output impedance mode that is suitable for bus speeds less than
800 megatransfers per second in some applications.
The maximum skew between any of the outputs is 150 ps at the ball grid array pin. The maximum intercon-
nect skew on the system board between any two outputs must be less than 150 ps. The interconnect skew on
the system board between any two inputs must be less than 300 ps.
Electrical and Thermal Characteristics
Page 30 of 78
Version 2.5
March 26, 2007
IBM [ IBM ]
