Datasheet
PowerPC 970FX RISC Microprocessor
Table 3-8. Clock ac Timing Specifications (Page 2 of 2)
Value
Callout
Characteristic
Number
Unit
Notes
Minimum
-0.3
Maximum
—
3
SYSCLK and SYSCLK input low voltage
Differential crossing-point voltage
Differential voltage
V
V
4
4
4
5
0.4 × OV
0.6 × OV
1.6
DD
DD
0.385
—
V
4, 7
4, 7
—
—
PLL lock time
800
μSec
—
—
Duty cycle
40%
60%
Notes:
1. Important: Processor frequency is determined by the PLL_MULT and SYSCLK input frequencies. PLL_RANGE(1:0) must be set
to the correct values for the expected processor frequency. Consult Table 5-2. PowerPC 970FX RISC Microprocessor PLL Config-
uration on page 64 for the allowable frequency range for these pins.
2. PowerPC 970FX minimum processor frequency will be determined by characterization. The minimum frequency is an estimation.
3. The rise and fall times for the SYSCLK inputs are measured from 0.4 to 1.0 V.
4. Important: The data in this table is based on simulation and might be revised after hardware characterization.
5. For a timing diagram, see Figure 3-1 on page 27.
6. Guaranteed by design and not tested.
7. The differential voltage is the minimum peak-to-peak voltage on both the SYSCLK and SYSCLK pins (similar to what is measured
with single-ended oscilloscope probes).
Figure 3-1. Clock Differential HSTL Signal
SYSCLK
5
2
4
SYSCLK
3
1
Notes:
The legend for this figure is provided by callout number in Table 3-8 on page 26.
To determine the processor clock, multiply the SYSCLK frequency by one of the following values:
• 12 for PLL_MULT = ‘0’
• 8 for PLL_MULT = ‘1’
For more information about the PLL configuration, see Table 5-2 PowerPC 970FX RISC Microprocessor PLL
Configuration on page 64.
Version 2.5
Electrical and Thermal Characteristics
Page 27 of 78
March 26, 2007
IBM [ IBM ]
