Datasheet
PowerPC 970FX RISC Microprocessor
3.1.4 dc Electrical Specifications
Table 3-4. dc Electrical Specifications
Voltage
Characteristic
Symbol
Unit
Notes
Minimum
Maximum
SYSCLK, SYSCLK input high voltage
SYSCLK, SYSCLK input low voltage
Processor interface (PI) input high voltage
PI input low voltage
—
—
0.7 × OV
OV + 0.3
V
V
1
1
DD
DD
-0.3
0.3 × OV
DD
V
(0.5 × OV ) + 0.2
—
V
2
IH
DD
V
—
(0.5 × OV ) - 0.2
V
2
IL
DD
NonPI input high voltage
V
0.7 × OV
—
V
3
IH
DD
NonPI input low voltage
V
—
0.3 × OV
V
3
IL
DD
PI output high voltage
V
0.78 × OV
—
V
4
OH
DD
PI output low voltage
V
—
0.22 × OV
V
4
OL
DD
NonPI output high voltage, I = -2 mA
V
OV - 0.2
—
0.2
0.2
0.2
60
V
—
—
5
OH
OH
DD
NonPI output low voltage, I = 2 mA
V
V
V
I
—
—
—
—
—
—
V
OL
OL
OL
OL
Open drain (OD) output low, I = 2 mA (CHKSTOP, I2CGO)
V
OL
OD output low, I = 5 mA (I2C)
V
OL
Input leakage current, V = OV
V
= 0 V
μA
μA
pF
—
—
6
IN
DD, IN
IN
Hi-Z (off state) leakage current, V
= OV
V
= 0 V
I
60
OUT
DD, OUT
TSO
Input capacitance, V = 0 V, frequency = 1 MHz
C
5.0
IN
IN
Notes: See Table 3-2 on page 21 for recommended operating conditions.
1. SYSCLK differential receiver requires high-speed transceiver logic (HSTL) differential signaling level. See the Joint Electron Device
Engineering Council (JEDEC) HSTL standard.
2. See the electrical interface section of the PowerPC 970FX RISC Microprocessor Users Manual. The minimum input must meet the
signal eye opening requirements of the link.
3. The Joint Test Action Group (JTAG) signals TDI, TMS, and TRST do not have internal pullups; therefore, pullups must be added to
the system board. Pullups should be added and adjusted according to the system implementation. These input and outputs meet
the dc specification in the JEDEC standard JESD8-11 for 1.5 V normal power supply range.
4. A 100 Ω split terminator is the test load. Note that a 40 Ω signal driver has an up level of 0.78 × OV for V and 0.22 × OV at
DD
OH
DD
V
.
OL
5. There are two open drain signals on this type of signal driver: CHKSTOP and I2CGO. The pullup for these nets depend on the T
rise
time requirement, net load, and topology. The following examples are two bounding suggestions based on a point-to-point 50 Ω net
with two lengths (5 cm and 61 cm). A 33 Ω series source terminator was added in both runs. A net of 61 cm is recommended.
Examples:
500 Ω pullup dc low level 0.18 V at the receiver
T
0.2 V - 0.8 V = 55 ns at 61 cm
rise
T
0.2 V - 0.8 V = 10 ns at 5 cm
rise
1 kΩ pullup dc low level 0.13 V at the receiver
T
0.2 V - 0.8 V = 115 ns at 61 cm
rise
T
0.2 V - 0.8 V = 20 ns at 5 cm
rise
6. Capacitance values are guaranteed by design and characterization, and are not tested.
Version 2.5
Electrical and Thermal Characteristics
Page 23 of 78
March 26, 2007
IBM [ IBM ]
