Data Sheet
Preliminary
PowerPC 970FX
Revision Log
Revision
Modification
Version 2.1
October 14, 2005
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Corrected F/2 values in Table 3-5. Power Consumption for Power-Optimized Parts
Enhanced descriptions within Section 4.2.2 Reduced-Lead Package Version
Version 2.0
Added information that describe the distinctive specifications of the Leaded package version and the Reduced-
Lead package version:
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Under Section 1.4 Ordering and Processor Version Register, added Leaded Package Version and
Reduced-Lead Package Version subsections.
Reorganized Section 3.1.5 Power Consumption, to provide power consumption information for both stan-
dard and power-optimized parts in Table 3-5, Table 3-6, Table 3-7 and Table 3-8.
Under Section 4.2 Mechanical Packaging, added Leaded Package Version and Reduced-Lead Package
Version subsections.
September 30, 2005
Updated Figure 5-1. PLL Power Supply Filter Circuit with current information and clarified several of the figure
callouts.
Version 1.0
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Updated Features listing, Table 1-1. Power PC 970FX Ordering and Processor Version Register (PVR) for
the Leaded PackageVersion and Figure 1-2 Part Number Legend
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Added errata list and application note documents to Related Publications
Updated some of the specifications in Table 3-2. Recommended Operating Conditions
Updated Section 3.1.5 Power Consumption, modifying content and form of specification tables.
Added note to Figure 3-3. Block Diagram of an SSB for a Processor Interconnect Implementation
Updated some of the specifications in Section 3.5.1.2 Drive Side Characteristics
Extensively updated specifications in Table 3-6. Power Consumption for Power-Optimized Parts and
Table 3-7. Power Consumption for Standard Parts
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Updated some of the specifications in Table 3-11. Processor Interconnect SSB Driver Specifications and
Table 3-13. Processor Interconnect SSB Receiver Specifications
Made major modifications to Table 3-12. Processor Interconnect SSB PCB Trace Specifications, Table 3-
14. Processor Interconnect SSB Timing Parameters for the Deskew and Clock Alignment and Section
3.5.1.4 Receive Side Characteristics
July 15, 2005
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Added Table 3-17. Input AC Timing Specifications for TBEN
Added clarifying note to Section 3.10.1 I2C Bus Timing Information
Clarified text in Section 3.10.3 I2C and JTAG Considerations
Updated some of the specifications in Figure 3-10. JTAG Clock Input Timing Diagram
Made major modifications to Section 3.10.3 I2C and JTAG Considerations, Section 5.7.1 Thermal Man-
agement pins, and Section 5.7.2 Reading Thermal Diode Calibration data via JTAG
Updated Section 4. PowerPC 970FX Microprocessor Dimension and Physical Signal Assignments to
describe both packaging types.
Changed titles for Figure 4-1. PowerPC 970FX Microprocessor for Mechanical Package, Leaded, for
DD3.0x Parts (top and side) and Figure 4-2. PowerPC 970FX Microprocessor Mechanical Package,
Leaded, for DD3.1x Parts (top and side)
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Updated Table 5-2. PowerPC 970FX PLL Configuration and Table 5-3. System Configuration - Typical
Examples of Pin Settings
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Added Table 5-9. Thermal Diode Data Encoding
Updated some of the specifications in Table 5-10. Allowable Forces on the PowerPC 970FX Package
Revision Log
October 14, 2005
Page 73 of 74
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