Data Sheet
PowerPC 970FX
Preliminary
Table 4-2. Pinout Listing for the CBGA Package (Continued)
I/O
EI/EO
Signal Name
Pin Number
Active
—
Notes
—
5
A1,A24,B7, B11, B16, B20, C2, C24, D9, E1, F3, F7, F19,
H24, J1, J8, J10, J14, J18, K5, K17, K21, L10, L16, M1,
M9, N24, P17, T11, T15, T21, W24, Y13, Y17, AA6, AA24,
AD1, AD9, AD15, AD19, AD23
OV
OV
DD
DD
Z_OUT
P2
R1
—
—
—
7
7
Z_SENSE
Notes:
—
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. These pins are reserved for potential future use.
3. TCK must be tied high or low for normal machine operation. If used, TDI, TMS, and TRST_B must be pulled up to OVDD
.
4. These are test signals for factory use only and must be pulled down with a 10K resistor to GND for normal machine operation.
5. I = Input, O = Output, EI = Elastic Input, EO= Elastic Output. For additional information, see the PowerPC 970FX RISC Micropro-
cessor Users Manual.
6. These pins may be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point immedi-
ately behind the module. They should not be connected to GND and VDD planes.
7. PSRO_ENABLE, Z_OUT, Z_SENSE, SPARE_GND, and SPARE2 are tied to GND.
8. CKTERM_DIS high disables SYSCLK termination.
9. If GPULDBG = 1 during HRESET transition from low to high: Run POR in debug mode and stop after each POR instruction.
If GPULDBG = 0 during HRESET transition from low to high: Run POR at once in automatic mode and not stop after each POR
instruction.
Toggling GPULDBG from 1 to 0 later on will exit POR debug mode and continue without stopping after each instruction.
10. The PLL_MULT and PLL_RANGE bits may be overwritten by JTAG commands and the BUS_CFG bits may be changed by SCOM
commands during the POR (power on reset) sequence. Refer to the POR Application Note for more details.
PowerPC 970FX Microprocessor Dimension and Physical
Signal Assignments
Page 54 of 74
October 14, 2005
IBM [ IBM ]
