Data Sheet
PowerPC 970FX
Preliminary
Table 4-2. Pinout Listing for the CBGA Package (Continued)
I/O
EI/EO
Signal Name
Pin Number
Active
Notes
5
LSSDMODE
AB5
U19
High
High
High
High
High
Low
High
—
Input
Input
Input
Input
Input
Input
4
4
LSSD_SCAN_ENABLE
LSSD_STOP_ENABLE
LSSD_STOPC2_ENABLE
AD11
AD8
4
4
LSSD_STOPC2STAR_ENABLE AD7
4
MCP_B
AD18
—
—
10
10
—
—
—
7
PLL_LOCK
PLL_MULT
PLL_RANGE(1:0)
PLLTEST
T20
Output
Input
Input
Input
Output
Input
—
AA8
AA9, AB7
—
W22
High
—
PLLTESTOUT
PROCID(0:2)
PSRO_ENABLE
PSRO0
T19
L19, M19, M18
—
V5
—
V23
—
Output
Input
Output
Input
Input
Output
Input
Input
Input
—
—
—
—
—
—
—
4
PSYNC
AA10
—
PSYNC_OUT
PULSE_SEL(0:2)
QACK_B
AD14
—
AC9, AB11, AC10
—
V21
AB12
AB6
AA5
AA13
W4
Low
Low
High
Low
—
QREQ_B
RAMSTOP_ENABLE
RI_B
1
SPARE
1, 2
7
SPARE2
—
SPARE_GND
SRESET_B
Notes:
N1
—
—
7
AB4
Low
Input
—
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. These pins are reserved for potential future use.
3. TCK must be tied high or low for normal machine operation. If used, TDI, TMS, and TRST_B must be pulled up to OVDD
.
4. These are test signals for factory use only and must be pulled down with a 10K resistor to GND for normal machine operation.
5. I = Input, O = Output, EI = Elastic Input, EO= Elastic Output. For additional information, see the PowerPC 970FX RISC Micropro-
cessor Users Manual.
6. These pins may be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point immedi-
ately behind the module. They should not be connected to GND and VDD planes.
7. PSRO_ENABLE, Z_OUT, Z_SENSE, SPARE_GND, and SPARE2 are tied to GND.
8. CKTERM_DIS high disables SYSCLK termination.
9. If GPULDBG = 1 during HRESET transition from low to high: Run POR in debug mode and stop after each POR instruction.
If GPULDBG = 0 during HRESET transition from low to high: Run POR at once in automatic mode and not stop after each POR
instruction.
Toggling GPULDBG from 1 to 0 later on will exit POR debug mode and continue without stopping after each instruction.
10. The PLL_MULT and PLL_RANGE bits may be overwritten by JTAG commands and the BUS_CFG bits may be changed by SCOM
commands during the POR (power on reset) sequence. Refer to the POR Application Note for more details.
PowerPC 970FX Microprocessor Dimension and Physical
Signal Assignments
Page 52 of 74
October 14, 2005
IBM [ IBM ]
