Data Sheet
Preliminary
PowerPC 970FX
Table 4-2. Pinout Listing for the CBGA Package (Continued)
I/O
EI/EO
Signal Name
Pin Number
Active
Notes
5
SRIN(0:1)
SRIN_B(0:1)
SROUT(0:1)
SROUT_B(0:1)
SYNC_ENABLE
SYSCLK
L24, L21
K24, L22
L3, G1
L2, F1
AB24
R22
—
—
Elastic Input
Elastic Input
Elastic Output
Elastic Output
Input
—
—
—
—
4
—
—
High
—
Input
—
—
—
3
SYSCLK_B
TBEN
T22
—
Input
AD17
AD21
AB21
AD13
V22
High
—
Input
TCK
Input
TDI
—
Input
3
TDO
—
Output
Input
—
—
3
THERM_INT_B
TMS
Low
—
AD22
N21
Input
TRIGGERIN
TRIGGEROUT
TRST_B
High
High
Low
Input
—
—
3
N19
Output
Input
W20
B3, B13, C20, D5, D7, D13, D17, D19, D21, D23, E4, E6,
E8, E10, E14, E16, E18, E22, F5, F9, F11, F13, F15, F17,
G6, G8, G10, G12, G14, G16, G18, G22, H5, H7, H9, H11,
H13, H15, H17, H19, J2, J4, J6, J12, J16, J20, K7, K9,
K11, K13, K15, K19, K23, L4, L6, L8, L12, L14, L18, L20,
M5, M7, M11, M13, M15, M17, M21, M23, N2, N4, N6, N8,
N10, N12, N14, N16, N18, N20, P1, P3, P5, P7, P9, P11,
P13, P15, P19, P21, P23, R4, R6, R8, R10, R12, R14,
R16, R18, T1, T3, T5, T7, T9, T13, T17, T23, U2, U4, U6,
U8, U10, U12, U14, U16, U18, U20, U22, V1, V3, V7, V9,
V11, V13, V15, V17, V19, W2, W6, W8, W10, W12, W14,
W16, W18, Y3, Y5, Y7, Y9, Y11, Y15, Y19, Y22, Y23, AA2,
AA4, AA16, AA18, AB1, AB3, AB9, AB13, AB15, AB17,
AB23, AC2, AC4, AC6, AC8, AC12, AC14, AC18, AC20,
AC22, AD3, AD5
V
—
V
—
DD
DD
Notes:
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. These pins are reserved for potential future use.
3. TCK must be tied high or low for normal machine operation. If used, TDI, TMS, and TRST_B must be pulled up to OVDD
.
4. These are test signals for factory use only and must be pulled down with a 10K resistor to GND for normal machine operation.
5. I = Input, O = Output, EI = Elastic Input, EO= Elastic Output. For additional information, see the PowerPC 970FX RISC Micropro-
cessor Users Manual.
6. These pins may be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point immedi-
ately behind the module. They should not be connected to GND and VDD planes.
7. PSRO_ENABLE, Z_OUT, Z_SENSE, SPARE_GND, and SPARE2 are tied to GND.
8. CKTERM_DIS high disables SYSCLK termination.
9. If GPULDBG = 1 during HRESET transition from low to high: Run POR in debug mode and stop after each POR instruction.
If GPULDBG = 0 during HRESET transition from low to high: Run POR at once in automatic mode and not stop after each POR
instruction.
Toggling GPULDBG from 1 to 0 later on will exit POR debug mode and continue without stopping after each instruction.
10. The PLL_MULT and PLL_RANGE bits may be overwritten by JTAG commands and the BUS_CFG bits may be changed by SCOM
commands during the POR (power on reset) sequence. Refer to the POR Application Note for more details.
PowerPC 970FX Microprocessor Dimension and Physical
October 14, 2005
Signal Assignments
Page 53 of 74
IBM [ IBM ]
