PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Pull-up Resistor Requirements
The 750 requires high-resistive (weak: 10KΩ) pull-up resistors on several control signals of the bus interface
to maintain the control signals in the negated state after they have been actively negated and released by the
750 or other bus masters. These signals are: TS, ABB, DBB, TBST, GBL, and ARTRY.
In addition, the 750 has one open-drain style output (CKSTP_OUT) that requires a pull-up resistor (weak or
strong: 4.7KΩ–1KΩ) if it is used by the system.
If address or data parity is not used by the system, it should be disabled using HID0. This also disables the
parity input receivers. In most systems, the unused (and disabled) parity pins can be left unconnected; how-
ever, in some systems, these parity pins must be pulled up to OVDD by a weak (or stronger) pull-up.
No pull-up resistors are normally required for the L2 interface, the 60x bus address and AP lines, or the 60x
bus data and DP lines. The data bus input receivers are normally turned off when no read operation is in
progress and do not require pull-up resistors on the data bus.
HRESET and GBL must be actively driven.
Resistor Pull-up / Pull-down Requirements
Required or Recommended Actions
Strong pull-up required
Signals
CKSTP_OUT
Weak pull-up required
TLBISYNC, LSSD_MODE, L1_TSTCLK, L2TSTCLK, TS, ABB, DBB, ARTRY,
GBL, TBST
Weak pull-up or pull-down required
Weak pull-up recommended
TCK
SRESET, SMI, INT, MCP, CKSTP_IN
AP[0:3], DP[0:3]
Weak pull-up recommended if pin not used
Page 43
Version 2.0
9/6/2002
IBM [ IBM ]
