PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Power and ground connections must be made to all external VDD, OVDD, and GND, pins of the 750.
External clock routing should ensure that the rising edge of the L2 clock is coincident at the CLK input of all
SRAMs and at the L2SYNC_IN input of the 750. The L2CLKOUTA network could be used only, or the
L2CLKOUTB network could also be used depending on the loading, frequency, and number of SRAMs.
Output Buffer DC Impedance
The 750 60x and L2 I/O drivers were characterized over process, voltage, and temperature. To measure Z0,
an external resistor is connected to the chip pad, either to OVDD or GND. Then the value of such resistor is
varied until the pad voltage is OVDD/2; see Figure 20, “Driver Impedance Measurement,” below.
The output impedance is actually the average of two components, the resistances of the pull-up and pull-
down devices. When Data is held low, SW1 is closed (SW2 is open), and RN is trimmed until Pad = OVDD/2.
RN then becomes the resistance of the pull-down devices. When Data is held high, SW2 is closed (SW1 is
open), and RP is trimmed until Pad = OVDD/2. RP then becomes the resistance of the pull-up devices. With a
properly designed driver RP and RN are close to each other in value, then Z0 = (RP + RN)/2.
Figure 20. Driver Impedance Measurement
OV
DD
RN
SW2
Pad
Data
SW1
RP
GND
The following table summarizes the impedance a board designer would design to for a typical process. These
values were derived by simulation at 65°C. As the process improves, the output impedance will be lower by
several ohms than this typical value.
Impedance Characteristics
VDD = 1.9V, L2OVDD=OVDD = 3.3V, TJ = 65°C
Process
Typical
60x
43
L2
38
Symbol
Z0
Unit
Ω
9/6/2002
Version 2.0
Page42
IBM [ IBM ]
