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IBM25PPC750L-EB0C366W 参数 Datasheet PDF下载

IBM25PPC750L-EB0C366W图片预览
型号: IBM25PPC750L-EB0C366W
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 366MHz, CMOS, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360]
分类和应用: 时钟外围集成电路
文件页数/大小: 46 页 / 610 K
品牌: IBM [ IBM ]
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PowerPC 750 SCM RISC Microprocessor  
PID8p-750  
Preliminary Copy  
AC Electrical Characteristics  
This section provides the AC electrical characteristics for the PID8p-750. After fabrication, parts are sorted by  
maximum processor core frequency as shown in the Section “Clock AC Specifications,” on page 10, and  
tested for conformance to the AC specifications for that frequency. These specifications are for 300MHz  
through 400MHz processor core frequencies. The processor core frequency is determined by the bus  
(SYSCLK) frequency and the settings of the PLL_CFG(0-3) signals. Parts are sold by maximum processor  
core frequency; see Section “Ordering Information,” on page 40.  
Clock AC Specifications  
The following table provides the clock AC timing specifications as defined in Figure 2.  
8
Clock AC Timing Specifications  
See Table “Recommended Operating Conditions1,2,3,” on page 6, for operating conditions.  
Num  
Characteristic  
300*, 333*, 350*, 366, 375MHz  
400, 433, 450, 466, 500MHz  
Unit Notes  
MHz  
Min  
Max  
Min  
Max  
Processor fre-  
quency  
200  
As per specified speed  
250  
As per specified speed  
SYSCLK frequency  
SYSCLK cycle time  
25  
10  
100  
40  
31  
10  
100  
32  
MHz  
ns  
1
1
2,3 SYSCLK rise and  
fall time  
1.0  
1.0  
ns  
2,3  
3,7  
4
SYSCLK duty cycle  
40  
60  
40  
60  
%
measured at OVDD  
2
/
SYSCLK jitter  
±150  
±150  
ps  
4,3  
5
Internal PLL relock  
time  
100  
100  
µs  
Note:  
1. Caution: The SYSCLK frequency and the PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) fre-  
quency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal  
description in Section “PLL Configuration,” on page 30 for valid PLL_CFG[0-3] settings.  
2. Rise and fall times for the SYSCLK input are measured from 0.5v to 1.5v  
3. Timing is guaranteed by design and characterization, and is not tested.  
4. The total input jitter (short term and long term combined) must be under ±150ps.  
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time required for PLL lock  
after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and  
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time  
during the power-on reset sequence.  
6. * Subject to availability - see your marketing representative.  
7. Duty cycle for 1.8, 2.5, and 3.3v I/Os.  
8. SYSCLK input levels must not be higher than the absolute maximum ratings table for VIN. See Table , “Absolute Maximum Ratings,” on page 6.  
Page 10  
Version 2.0  
Datasheet  
9/30/99  
 
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