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IBM25PPC750L-EB0C366W 参数 Datasheet PDF下载

IBM25PPC750L-EB0C366W图片预览
型号: IBM25PPC750L-EB0C366W
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 366MHz, CMOS, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360]
分类和应用: 时钟外围集成电路
文件页数/大小: 46 页 / 610 K
品牌: IBM [ IBM ]
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PowerPC 750 SCM RISC Microprocessor  
PID8p-750  
Preliminary Copy  
Electrical and Thermal Characteristics  
This section provides both AC and DC electrical specifications and thermal characteristics for the PID8p-750.  
DC Electrical Characteristics  
The tables in this section describe the PID8p-750’s DC electrical characteristics. The following table provides  
the absolute maximum ratings.  
Absolute Maximum Ratings  
Characteristic  
Symbol  
VDD  
Value  
Unit  
V
Core supply voltage  
-0.3 to 2.5  
-0.3 to 2.5  
-0.3 to 2.5  
-0.3 to 3.6  
-0.3 to 2.8  
-0.3 to 2.1  
-0.3 to 3.6  
-0.3 to 3.6  
-0.3 to 2.8  
-0.3 to 2.1  
-55 to 150  
PLL supply voltage  
AVDD  
V
L2 DLL supply voltage  
60x bus supply voltage (maximum)  
L2AVDD  
OVDD(3.3V)  
OVDD(2.5V)  
OVDD(1.8V)  
L2OVDD  
VIN(3.3V)  
VIN(2.5V)  
VIN(1.8V)  
TSTG  
V
V
L2 bus supply voltage (maximum)  
Input voltage (maximum)  
V
V
Storage temperature range  
°C  
Note:  
1. Functional and tested operating conditions are given in Table ”Recommended Operating Conditions1,2,3,” below. Absolute maximum ratings are  
stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause per-  
manent damage to the device.  
2. Caution: VIN must not exceed OVDD by more than 0.3V at any time, including during power-on reset.  
3. Caution: OVDD/ L2OVDD must not exceed VDD/AVDD by more than 2.0V during normal operation. On power up and power down, OVDD/ L2OVDD must not  
exceed VDD/AVDD by more than 3.3V and for no more than 20ms.  
4. Caution: VDD/AVDD must not exceed OVDD/ L2OVDD by more than 0.4V during normal operation. On power up and power down, VDD/AVDD must not  
exceed OVDD/ L2OVDD by more than 1.0V and for no more than 20ms.  
The following table provides the recommended operating conditions for the PID8p-750.  
1,2,3  
Recommended Operating Conditions  
Characteristic  
Symbol  
VDD  
Value  
Unit  
V
Core supply voltage  
2.0 to 2.1  
PLL supply voltage  
AVDD  
2.0 to 2.1  
V
L2 DLL supply voltage  
L2AVDD  
OVDD(3.3V)  
OVDD(2.5V)  
OVDD(1.8V)  
L2OVDD(3.3V)  
2.0 to 2.1  
V
60x bus supply voltage, pin W1 tied high  
60x bus supply voltage, pin W1 tied to HRESET  
60x bus supply voltage, pin W1 tied to GND  
L2 bus supply voltage, pin A19 tied high  
Note:  
3.135 to 3.465  
2.375 to 2.625  
1.71 to 1.89  
3.135 to 3.465  
V
V
V
V
1. These are recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.  
2. For dd3.x, If W1 is left unconnected, the 60X bus will default to OVDD = 3.3V. For dd2x, W1=Don’t care  
3. For dd3.x, If A19 is left unconnected, the L2 bus will default to L2OVDD = 3.3V. For dd2x, W1=Don’t care  
Page 6  
Version 2.0  
Datasheet  
9/30/99  
 
 
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