Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
5.9.4.2 Processor Debug System Enablement when Implementing Precharge Selection
System designers who want to use a processor debug system attached to the 750GX IEEE 1149.1 test
access port (TAP) interface (such as the IBM RISCWatch debug system) should provide a method to assert
QACK after the transition of HRESET. Debug systems use a “soft stop” feature to stop the processor, allow
processor internal states to be read, and then restart of the processor. A soft stop requires the system to be in
a quiescent state before the processor can be queried for internal state values. This is accomplished by the
assertion of a quiescent request (that is, QREQ is asserted) and subsequent acknowledgement (that is,
QACK is asserted). Systems that do not use the power management features; doze, nap, and sleep; and do
not require the extended pre-charge feature can drive the QACK pin with an inverted version of HRESET.
750GX_ds_body.fm SA14-2765-02
September 2, 2005
System Design Information
Page 71 of 73
IBM [ IBM ]
