Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
Though the junction-to-ambient and the heat-sink-to-ambient thermal resistances are a common
figure-of-merit used for comparing the thermal performance of various microelectronic packaging technolo-
gies, one should exercise caution when only using this metric in determining thermal management because
no single parameter can adequately describe three-dimensional heat flow. The final chip-junction operating
temperature is not only a function of the component-level thermal resistance, but the system-level design and
its operating conditions. In addition to the component's power dissipation, a number of factors affect the final
operating die-junction temperature. These factors might include air flow, board population (local heat flux of
adjacent components), heat-sink efficiency, heat-sink attach, next-level interconnect technology, system air
temperature rise, and so forth.
5.9 Operational and Design Considerations
5.9.1 Level Protection
A level protection feature is included in the IBM PowerPC 750GX RISC Microprocessor. The level protection
feature is available in the 1.8 V, 2.5 V, and 3.3 V bus modes. This feature prevents ambiguous floating refer-
ence voltages by pulling the respective signal line to the last valid or nearest valid state.
For example, if the input/output voltage level is closer to OVDD, the circuit pulls the I/O level to OVDD. If the I/O
level is closer to GND, the I/O level is pulled low. This self-latching circuitry keeps the floating inputs defined
and avoids meta-stability. In Table 5-6, Input/Output Usage, on page 57, these signals are defined as
“keeper” in the “Level Protect” column.
The level protect circuitry provides no additional leakage current to the signal I/O; however, some amount of
current must be applied to the keeper node to overcome the level protection latch. This current is process
dependent, but in no case is the current required over 100 µA.
This feature allows the system designer to limit the number of resistors in the design and optimize placement
and reduce costs.
Note: Having a keeper on the associated signal I/O does not replace a pull-up or pull-down resistor that is
needed by a separate device located on the 60x bus. The designer must supply any termination requirements
for these separate devices, as defined in their specifications.
5.9.2 64-Bit or 32-Bit Data Bus Mode
The typical operation for the 750GX DD1.X revision level is considered to be in 64-bit data bus mode. Mode
setting is determined by the state of the mode signal, TLBISYNC, at the transition of HRESET from its active
to inactive state (low to high). If TLBISYNC is high when HRESET transitions from active to inactive, 64-bit
mode is selected. If TLBISYNC is low when HRESET transitions from active to inactive, 32-bit mode is
selected.
Special Note: (Reduced pin out mode) To transition from a previous processor with reduced pin out mode,
the customer will need to drive TLBISYNC appropriately, leave the DP(0..7) and AP(0..3) pins
floating, and disable parity checking with the HID0 bits. The 750GX, like the 750FX, 750CXe,
and 750, does not have APE and DPE pins.
750GX_ds_body.fm SA14-2765-02
September 2, 2005
System Design Information
Page 69 of 73
IBM [ IBM ]
