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IBM25PPC750GXECB5H83T 参数 Datasheet PDF下载

IBM25PPC750GXECB5H83T图片预览
型号: IBM25PPC750GXECB5H83T
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 933MHz, CMOS, CBGA292, 21 X 21 MM, 1 MM PITCH, CERAMIC, BGA-292]
分类和应用: 时钟外围集成电路
文件页数/大小: 74 页 / 1054 K
品牌: IBM [ IBM ]
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Datasheet  
IBM PowerPC 750GX RISC Microprocessor  
DD1.X  
5.9.3 I/O Voltage Mode Selection  
Selection between 1.8 V, 2.5 V, or 3.3 V I/O modes is accomplished by using the BVSEL and L1_TSTCLK  
pins:  
• If BVSEL = 1 and L1_TSTCLK = 0, then the 3.3 V mode is enabled.  
• If BVSEL = 1 and L1_TSTCLK = 1, then the 2.5 V mode is enabled.  
• If BVSEL = 0 and L1_TSTCLK = 1, then the 1.8 V mode is enabled.  
Note: Do not set BVSEL = 0 and L1_TSTCLK = 0 since it yields an invalid mode.  
Table 5-10. Summary of Mode Select  
Mode  
750GX  
Sample TLBISYNC to select  
High = 64-bit mode  
32-bit mode  
Low = 32-bit mode  
Selects DRTRY mode.  
Data retry mode  
0 at HRESET transition  
1 at HRESET transition  
No DRTRY mode  
DRTRY mode  
Factory usage modes are selected by sensing the data bus disable (DBDIS),  
data bus write-only (DBWO), and L2_TSTCLK pins at the transition of  
HRESET from low to high. These pins should be held inactive (high) at the  
HRESET transition for normal machine operation.  
Factory usage modes  
3.3 V 165 mV (BVSEL = 1, L1_TSTCLK = 0) or  
2.5 V 125 mV (BVSEL = 1, L1_TSTCLK = 1) or  
1.8 V 100 mV (BVSEL = 0, L1_TSTCLK = 1)  
I/O mode selection  
QACK in a logical high state at the transition of HRESET from asserted to  
negated enables standard precharge mode, the recommended default. See  
Section 5.9.4.1 for details.  
Standard/extended precharge mode  
5.9.4 QACK Signal Implementation for Selected Features  
5.9.4.1 Precharge Duration Selection and Application  
An extended precharge feature is available for the signals ABB, DBB, and ARTRY in situations where the  
loading and net topology of these signals requires a longer precharge duration for the signals to attain a valid  
level.  
This feature has not been fully tested and should not be necessary in a properly designed system, even at  
200 MHz. System designers should assume standard precharge as the default selection, with an option to  
use extended precharge.  
The bus signals, ABB, DBB, and ARTRY, require a precharge to the inactive state (bus high) before going to  
tristate. The precharge duration in standard precharge mode is approximately one half cycle, and should be  
used for systems with point-to-point topologies. Extended precharge mode increases the precharge duration  
to one cycle. This increase may be required for bus speeds approaching 200 MHz when bus loading is high.  
QACK in a logical high state at the transition of HRESET from asserted to negated enables standard pre-  
charge mode in the 750GX. QACK in a logical low state at the transition of HRESET from asserted to negated  
enables extended pre-charge mode in the 750GX.  
System Design Information  
Page 70 of 73  
750GX_ds_body.fm SA14-2765-02  
September 2, 2005