Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
1.2 Design Highlights
The 750GX supports several unique features including:
• Pin compatible with the PowerPC 750FX RISC Microprocessor
• 1-MB L2 cache, 4-way set associative, operating at core frequency
• Independent L2 cache locking of all four ways
• L2 cache may be configured to contain instructions only or data only
• Enhanced 60× bus to support up to five pipelined transactions
• Up to 1-GHz operation at embedded application specifications
1.3 Processor Version Register
The IBM PowerPC 750GX RISC Microprocessor has the following processor version register (PVR) values
for the respective design revision levels.
Table 1-1. 750GX Processor Version Register (PVR)
750GX Design Revision Level
750GX PVR
0x700201r0
0x700201r1
0x700201r2
DD1.0
DD1.1
DD1.2
Note: r = reserved nibble; reserved bits can be either '0' or '1', and should be masked in application software.
750GX_ds_body.fm SA14-2765-02
September 2, 2005
General Information
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