Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
• System unit
– Ability to restrict the cache for instruction-
only or data-only operation
– Copy-back or write-through data cache on a
page basis, or for entire L2 cache
– 64-byte sectored line size
– Executes Condition Register (CR) logical
instructions and miscellaneous system
instructions
– Special register transfer instructions
– L2 frequency at core speed
– Error checking and correction (ECC) protec-
tion on SRAM array
– Parity on L2 tags
– Supports up to four outstanding misses (four
data or three data and one instruction)
• Level 1 (L1) cache structure
– 32-KB, 8-way set associative instruction and
data caches
– Single-cycle cache access
– Pseudo-least-recently-used (PLRU)
replacement
– Cache write-back or write-through opera-
tions programmable on a virtual-page or
BAT-block basis
– Parity on L1 tags and caches
– 3-state modified/exclusive/invalid (MEI)
memory coherency
• Power
– Low power consumption with low voltage
application at lower frequency
– Dynamic power management
– Three static power save modes: doze, nap,
and sleep
– Hardware support for data coherency
– Non-blocking instruction cache (one out-
standing miss)
– Non-blocking data cache (four outstanding
misses)
– Thermal assist unit (TAU)
• Bus interface
– 32-bit address bus
– 64-bit data bus (also supports 32-bit mode)
– Up to 200-MHz 60x bus frequency
– Four load/store requests, plus one snoop
are supported for a total of five outstanding
bus requests. Load/store requests can be a
combination of three data and one instruc-
tion, or four data requests
– Core-to-bus multipliers are supported in
half-step integer increments from 2 through
10, and in full-step increments from 10
through 20. Ratios of 3.5x and lower are not
supported with miss-under-miss enabled
– Supports 1.8-V, 2.5-V, or 3.3-V I/O modes
– No snooping of instruction cache
• Memory management unit
– 64-entry, 2-way set associative instruction
TLB (total 128)
– 64-entry, 2-way set associative data TLB
(total 128)
– Hardware reload for TLBs
– Eight instruction block address translation
(BAT) arrays and eight data BAT arrays
– Virtual memory support for up to 4 exabytes
(252) virtual memory
– Real memory support for up to 4 gigabytes
(232) of physical memory
• Reliability and serviceability
– Parity checking on 60× bus interface
– ECC detection and correction on L2 cache
– Parity on the L1 caches
– Support for big-endian/little-endian address-
ing
• Dual phase-locked loops (PLLs)
– Parity on the L1 and L2 tags
– Allow seamless frequency switching
• Testability
• Level 2 (L2) cache
– Level-sensitive scan design (LSSD) testing
– Powerful diagnostic and test interface
through Common On-Chip Processor (COP)
and IEEE 1149.1 (JTAG) interface
– Integrated 1-MB L2 cache with on-chip con-
troller and 8-KB entry tags
– 4-way set-associative; supports locking by
way
General Information
Page 10 of 73
750GX_ds_body.fm SA14-2765-02
September 2, 2005
IBM [ IBM ]
