Preliminary
PowerPC 750FL RISC Microprocessor
Figure 5-7. IBM RISCWatch JTAG to HRESET, TRST, and SRESET Signal Connector
HRESET from RISCWatch
HRESET to PowerPC 750FL
System HRESET
TRST to PowerPC 750FL
TRST from RISCWatch
SRESET from RISCWatch
SRESET to PowerPC 750FL
System SRESET
Note: See notes for Table 5-6 Input/Output Use on page 51.
5.5 Level Protection
A level protection feature is included in the 750FL microprocessor. The level protection feature is available in
the 1.8 V, 2.5 V, and 3.3 V bus modes. This feature prevents ambiguous floating reference voltages by
pulling the respective signal line to the last valid or nearest valid state.
For example, if the I/O voltage level is closer to OVDD, the circuit pulls the I/O level to OVDD. If the I/O level is
closer to GND, the I/O level is pulled low. This self-latching circuitry keeps the floating inputs defined and
prevents metastability. In Table 5-6 Input/Output Use on page 51, these signals are defined as keeper in the
Level Protect column.
Keepers are not intended to force a net to a particular state. The keeper supplies a small (100 μA maximum)
amount of current, which is intended to help keep a net at the current logic state.
The level protect circuitry provides no additional leakage current to the signal I/O; however, some amount of
current must be applied to the keeper node to overcome the level protection latch. This current is process
dependent, but in no case is the current required over 100 μA.
This feature allows the system designer to limit the number of resistors in the design, optimize placement,
and reduce costs.
Note: Having a level protection (keeper) on the associated signal I/O does not replace a pull-up or pull-down
resistor that is needed by the 750FL microprocessor or a separate device located on the 60x bus. The
designer must supply any such resistors.
750flds60.fm.6.0
April 27, 2007
System Design Information
Page 55 of 65
IBM [ IBM ]
