Preliminary
PowerPC 750FL RISC Microprocessor
Table 4-1. Pinout Listing for the CBGA Package (Sheet 2 of 3)
Signal Name
Pin Number
Active
Low
Input/Output
Input/Output
Notes
GBL
W1
B2, B19, C5, C8, C13, C16, D10, D11, E3, E7, E14,
E18, F10, F11, G5, G8, G13, G16, H3, H8, H9, H12,
H13, H18, J12, K4, K7, K10, K14, K17, L4, L7, L10,
L14, L17, M12, N3, N8, N9, N12, N13, N18, P5, P8.
P13, P16, R10, R11, T3, T7, T14, T18, U10, U11, V5,
V8, V13,V16, W2, W19,
GND
HRESET
INT
Y11
Y9
Low
Low
High
High.
Low
Low
Input
Input
Input
Input
Input
Input
L1_TSTCLK
L2_TSTCLK
LSSD_MODE
MCP
Y13
W13
U13
W12
4
1
1
C4, C7, C14, C17, D3, D18, E10, E11, G3, G7, G14,
G18, H5, H16, K5, K16, L5, L16, N5, N16, P3, P7, P14,
P18, T10, T11, U3, U18, V4, V7, V14, V17
OVDD
2
PLL_CFG[0:4]
PLL_RNG[0:1]
QACK
QREQ
RSRV
Y18, W17, Y17, U16, W14
High
High
Low
Low
Low
Low
Low
High
Low
High
Low
High
High
High
Low
Low
High
Low
Input
Input
W15, U14
Y8
Input
U8
Output
Output
Input
Y4
SMI
W10
Y7
SRESET
SYSCLK
TA
Input
W16
A12
W8
Input
Input
TBEN
Input
TBST
A11
T2
Input/Output
Input
TCK
5
TDI
V2
Input
TDO
W5
Output
Input
TEA
W6
TLBISYNC
TMS
W11
V1
Input
Input
TRST
U1
Input
Notes:
1. These are test signals for factory use only and must be pulled up to OVDD for normal system operation.
2. OVDD supplies power to the input/output drivers and VDD supplies power to the processor core.
3. These pins are reserved.
4. BVSEL and L1_TSTCLK select the input/output voltage mode on the 60x bus (see Section 5.7 I/O Voltage Mode Selection on
page 56).
5. TCK must be tied high or low for normal system operation.
6. Address and data parity must be left floating if unused in the design.
750flds60.fm.6.0
April 27, 2007
Dimensions and Signal Assignments
Page 33 of 65
IBM [ IBM ]
