PowerPC 750FL RISC Microprocessor
Preliminary
Table 4-1. Pinout Listing for the CBGA Package (Sheet 3 of 3)
Signal Name
Pin Number
Active
Low
Input/Output
Input/Output
Output
Notes
TS
B15
TSIZ[0:2]
TT[0:4]
A14, B12, B11
High
High
D14, B17, B14, A15, B13
Input/Output
C10, C11, E8, E13, F6, F9, F12, F15, J8, J9, J13, K3,
K8, K11, K13, K18, L3, L8, L11, L13, L18, M8, M9,
M13, R6, R9, R12, R15, T8, T13, V10, V11
VDD
2
WT
U5
Low
Output
Notes:
1. These are test signals for factory use only and must be pulled up to OVDD for normal system operation.
2. OVDD supplies power to the input/output drivers and VDD supplies power to the processor core.
3. These pins are reserved.
4. BVSEL and L1_TSTCLK select the input/output voltage mode on the 60x bus (see Section 5.7 I/O Voltage Mode Selection on
page 56).
5. TCK must be tied high or low for normal system operation.
6. Address and data parity must be left floating if unused in the design.
Dimensions and Signal Assignments
Page 34 of 65
750flds60.fm.6.0
April 27, 2007
IBM [ IBM ]
