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IBM25PPC750FL-GR0133T 参数 Datasheet PDF下载

IBM25PPC750FL-GR0133T图片预览
型号: IBM25PPC750FL-GR0133T
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 600MHz, CMOS, CBGA292, 21 X 21 MM, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, BGA-292]
分类和应用: 时钟外围集成电路
文件页数/大小: 66 页 / 1860 K
品牌: IBM [ IBM ]
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PowerPC 750FL RISC Microprocessor  
Preliminary  
3.5 60x Bus Output ac Specifications  
Table 3-9 provides the 60x bus output ac timing specifications for the 750FL microprocessor as defined and  
defined in Figure 3-6 Output Timing Diagram for PowerPC 750FL RISC Microprocessor on page 26.  
Table 3-9. 60x Bus Output ac Timing Specifications 1, 5, 8  
1.8 V Mode  
2.5 V Mode  
3.3 V Mode  
Reference  
Number  
Characteristic  
Unit Notes  
ns  
Minimum  
Maximum  
Minimum  
Maximum  
Minimum  
Maximum  
SYSCLK to output driven  
(Output Enable Time)  
12  
13  
14  
0.3  
0.5  
0.3  
0.3  
SYSCLK to output valid  
2.3  
2.5  
2.5  
ns  
ns  
2, 6  
2, 7  
SYSCLK to output invalid  
(Output Hold)  
0.55  
0.55  
SYSCLK to output high  
impedance (all signals  
except ARTRY, ABB and  
DBB)  
15  
2.5  
2.5  
2.5  
ns  
SYSCLK to ABB and DBB  
high impedance after pre-  
charge  
16  
17  
1.0  
3.0  
1.0  
3.0  
1.0  
3.0  
tSYSCLK 3, 4  
SYSCLK to ARTRY  
high impedance  
ns  
before precharge  
SYSCLK to ARTRY pre-  
charge enable  
0.2 ×  
tSYSCLK + 1.0  
0.2 ×  
tSYSCLK + 1.0  
0.2 ×  
tSYSCLK + 1.0  
18  
19  
ns  
2, 3, 4  
MaximumdelaytoARTRY  
precharge  
1.0  
2.0  
1.0  
2.0  
1.0  
2.0  
tSYSCLK 3, 4  
SYSCLK to ARTRY  
high impedance  
after precharge  
20  
tSYSCLK 3, 4  
Notes:  
1. All output specifications are measured from the VM of the rising edge of SYSCLK to the output signal level defined in Figure 3-5  
Output Valid Timing Definition on page 25. Both input and output timings are measured at the pin. Timings are determined by  
design.  
2. This minimum parameter assumes CL = 0 pF.  
3. tSYSCLK is the period of the external bus clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of  
SYSCLK to compute the actual time duration (in ns) of the parameter in question.  
4. Nominal precharge width for ARTRY is 1.0 tSYSCLK  
.
5. Guaranteed by design and characterization and not tested.  
6. Output valid timing increases as the VDD in reduced. These values assume a minimum VDD of 1.35 V.  
7. See Section 3.6 Alternate I/O Timing for 3.3 V Bus on page 26.  
8. See Table 3-2 Recommended Operating Conditions on page 17 for operating conditions.  
Electrical and Thermal Characteristics  
Page 24 of 65  
750flds60.fm.6.0  
April 27, 2007