PowerPC 750FL RISC Microprocessor
Preliminary
Figure 3-6. Output Timing Diagram for PowerPC 750FL RISC Microprocessor
VM
VM
VM
SYSCLK
SYSCLK
SYSCLK
SYSCLK
13
14
15
All Outputs
(Except TS,
ARTRY)
12
VM
VM
13
14
15
13
TS
VM
16
ABB, DBB
20
19
18
17
ARTRY
High Level
Hi-Z
Low Level
Note: SYSCLK VM is defined in Section 3.2 Clock ac Specifications on page 20. Output VM is defined in Section 3-5 Output Valid
Timing Definition on page 25.
3.6 Alternate I/O Timing for 3.3 V Bus
An alternate I/O timing specification can be used for DD2.3 when the following conditions exist:
• OV
= 3.3 V 5%
DD
• V = 1.45 V +/− 50 mV
DD
• T = -40°C − 105°C
j
All other recommended operating conditions are described in Table 3-2 Recommended Operating Conditions
on page 17.
The following alternate I/O timing specifications can be used under the previous conditions:
1. Consider V = 1/2 (OV ) for SYSCLK, input timing, and output timings.
M
DD
2. Input hold (T11a) becomes 250 ns minimum for 3.3 V. Output hold (T14) becomes 650 ns minimum for
3.3 V.
3. All other timing specifications are unchanged.
Electrical and Thermal Characteristics
Page 26 of 65
750flds60.fm.6.0
April 27, 2007
IBM [ IBM ]
