Preliminary
PowerPC 750FL RISC Microprocessor
3.3 Spread Spectrum Clock Generator
When designing with the spread spectrum clock generator (SSCG), there are a number of design issues that
must be taken into account.
SSCG creates a controlled amount of long-term jitter. In order for a receiving PLL in the 750FL micropro-
cessor to operate in this environment, it must be able to accurately track the SSCG clock jitter.
The accuracy to which the 750FL PLL can track the SSCG clock is referred to as tracking skew. When
performing system timing analysis, the tracking skew must be added to or subtracted from the I/O timing
specifications because the tracking skew appears as a static phase error between the internal PLL and the
SSCG clock.
To minimize the impact on I/O timings the following SSCG configuration is recommended:
• Down-spread mode, less than or equal to 1% of the maximum frequency
• A modulation frequency of 30 kHz
1
• Linear sweep modulation or “Hershey Kiss” (as in a Lexmark profile) modulation profile as shown in
Figure 3-2.
In this configuration, the tracking skew is less than 100 ps.
Figure 3-2. Linear Sweep Modulation Profile
0%
Down spread
frequency
change
-1%
0 μs
33.3 μs
Time Increases
1. See patent 5,631,920.
750flds60.fm.6.0
April 27, 2007
Electrical and Thermal Characteristics
Page 21 of 65
IBM [ IBM ]
