Preliminary
PowerPC 750FL RISC Microprocessor
3.6.1 IEEE 1149.1 ac Timing Specifications
The five Joint Test Action Group (JTAG) signals are test data in (TDI), test data out (TDO), test mode select
(TMS), test clock (TCK), and test reset (TRST). Unless otherwise noted, JTAG specifications are referenced
to GND and OV . The JTAG I/Os are powered by OV
.
DD
DD
Table 3-10. JTAG ac Timing Specifications (Independent of SYSCLK) 6
Reference
Number
Characteristic
TCK frequency of operation
Minimum.
Maximum
25
Unit
Notes
0
40
15
0
MHz
ns
1
2
TCK cycle time
TCK clock pulse width measured at 1.1 V
TCK rise and fall times
ns
3
2
ns
4
4
Specification obsolete, intentionally omitted
TRST assert time
5
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
6
Boundary-scan input data setup time
Boundary-scan input data hold time
TCK to output data valid
7
13
2
8
8
3, 5
3, 4
9
TCK to output high impedance
TMS, TDI data setup time
3
0
19
10
11
12
13
14
TMS, TDI data hold time
15
2.0
3
TCK to TDO data valid
12
9
5
4
TCK to TDO high impedance
TCK to output data invalid (output hold)
0
–
Notes:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. The non-JTAG signal input timing is measured with respect to TCK.
3. The non-JTAG signal output timing is measured with respect to TCK.
4. Guaranteed by characterization and not tested.
5. The minimum specification is guaranteed by characterization and not tested.
6. See Table 3-2 Recommended Operating Conditions on page 17 for operating conditions.
Figure 3-7. JTAG Clock Input Timing Diagram
1
2
2
TCK
VM
VM
VM
3
3
VM = Midpoint Voltage (OVDD/2)
750flds60.fm.6.0
April 27, 2007
Electrical and Thermal Characteristics
Page 27 of 65
IBM [ IBM ]
