DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
Figure 3-6. Output Timing Diagram for PowerPC 750FX RISC Microprocessor
VM
VM
VM
SYSCLK
SYSCLK
SYSCLK
SYSCLK
13
14
15
All Outputs
(Except TS,
ARTRY)
12
VM
VM
13
14
15
13
TS
VM
16
ABB, DBB
20
19
18
17
ARTRY
High Level
Hi-Z
Low Level
Note: SYSCLK VM as defined in Section 3.2 Clock AC Specifications on page 13. Output VM as defined in Section 3-5 Output Valid
Timing Definition on page 18.
3.6 Alternate I/O Timing For 3.3V Bus
An alternate I/O timing specification may be used for dd2.3, where:
• OV = 3.3V +/- 5%,
DD
• V = 1.45V +/- 50mV, and
DD
0
0
• T = -40 C to 105 C.
j
• All other recommended operating conditions are as per Table 3-2.
The following alternate I/O timing specifications may be used under the above conditions:
1. Consider V = 1/2 (OV ) for SYSCLK, input timing, and output timings.
M
DD
2. Input hold (T11a) becomes 250 ns minimum for 3.3V. Output hold (T14) becomes 650 ns minimum for
3.3V.
3. All other timing specifications are unchanged.
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
3. Electrical and Thermal Characteristics
Page 19 of 63
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