DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
3.4 60x Bus Input AC Specifications
Table 3-7. 60x Bus Input Timing Specifications
See Table 3-2 on page 10 for operating conditions.1,5
1.8V Mode
2.5V Mode
3.3V Mode
Num
Characteristic
Unit
ns
Notes
—
Min.
1.0
Max.
Min.
1.5
Max.
Min.
1.8
Max.
10a All inputs valid to SYSCLK (input setup)
—
—
INT_, SMI_, MCP, TBEN, DRTRY, and TLBISYNC
(input setup)
10b
1.5
1.5
1.8
Mode select input setup to HRESET
(TLBISYNC, DRTRY)
10c
8
—
—
8
—
—
8
—
—
t
2, 3, 4, 5
6
SYSCLK
11a SYSCLK to inputs invalid (input hold)
0.65
1.5
0.65
2.5
0.55
2.5
ns
INT_, SMI_, MCP, TBEN, DRTRY, and TLBISYNC
(input hold)
11b
ns
HRESET to mode select input hold
(TLBISYNC, DRTRY)
11c
0
—
0
—
0
—
ns
—
2, 4, 5
—
VM Measurement Reference Voltage for Inputs
OV /2
DD
Notes:
1. Input specifications are measured from the VM of the signal in question to VM of the rising edge of the input SYSCLK. Input and
output timings are measured at the pin (see Figure 3-3).
2. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3-4 on page 16).
3. t
, is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by
SYSCLK
the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255
bus clocks after the PLL relock time during the power-on reset sequence.
5. All values are guaranteed by design, and are not tested.
6. See Alternate I/O Timing For 3.3V Bus on page 19
Figure 3-3 provides the input timing diagram for the 750FX.
Figure 3-3. Input Timing Diagram
VMsysclk(0.65V)
SYSCLK
10a
10b
11a
11b
ALL INPUTS
VM
VM
VM = Midpoint Voltage (OV /2)
DD
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
3. Electrical and Thermal Characteristics
Page 15 of 63
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