DD 2.X
PowerPC 750FX RISC Microprocessor
Preliminary
2.2 General Parameters
Table 2-1 provides a summary of the general parameters of the 750FX.
Table 2-1. 750FX General Parameters
Item
Description
Notes
Technology
Die Size
0.13µm CSOI technology, six-layer metallization plus one level of local interconnect
34.3 sq. mm
Transistor count
Logic design
38 million - including L2 cache
Fully-static
292-pin ceramic ball grid array (CBGA)
21x21mm (1.0 mm pitch)
0.8 mm ball size
Package
Core power supply
I/O power supply
Note:
1.45V +/- 50 mV
1
2
3.3V +/- 165mV (BVSEL = 1, L1_TSTCLK = 0) or
2.5V +/- 125mV (BVSEL = 1, L1_TSTCLK = 1) or
1.8V +/- 100mV (BVSEL = 0, L1_TSTCLK = 1)
1. In some cases, when using 1.8v or 2.5v IO mode, it is possible to reduce power dissipation by lowering the core power supply volt-
age. See the Datasheet Supplement for details.
2. BVSEL =0, L1_TSTCLK = 0 is an INVALID setting. DD2.0 supports only a limited use of 3.3v IO mode. See the 750FX Errata List
for revision DD2.x for more information.
2. Overview
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
Page 8 of 63
IBM [ IBM ]
