DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
1.2 Design Level Considerations and Features
The 750FX supports several unique features including those listed below. The IBM application note Differ-
ences between the PowerPC 750FX, 750, 750CX, and 750CXe Microprocessors provides a more detailed
explanation of these features.
• Incorporates an on-chip, 512K, two-way, set-associative L2 cache
• Provides a 64 or 32-bit Data Bus mode (per setup of TLBISYNC pin)
• Supports 1.8V, 2.5V, or 3.3V I/O modes
Implementation Note: DD2.0 supports a limited use of the 3.3V I/O mode. For additional
information, see the 750FX Errata List of Revision DD2.X.
• Includes all 60x bus pins on earlier PowerPC 750 designs and additional signals
• Enhanced 60x bus — for pipelined consecutive read transactions and higher frequency operation
• Dual PLLs for additional power savings capabilities
• Four additional IBAT/DBAT registers
• New CBGA package with additional pins and depopulated footprint
1.3 Processor Version Register
The PowerPC 750FX RISC Microprocessor has the following Processor Version Register (PVR) values for
the respective design revision levels.
The 750FX PVR is 7000, which is not used in any previous PowerPC processor design.
Table 1-1. 750FX Processor Version Register (PVR)
750FX Design Revision Level
750FX PVR
0x700a02b0
0x700a02b1
0x700a02b2
0x700a02b3
DD2.0
DD2.1
DD2.2
DD2.3
Note:
1. Nibbles shown as ‘b’ are to be ignored, and are for factory use only. Nibbles shown as ‘a’ may be 0 or 1
2. If L2_TSTCLK is pulled low, the PVR may read 0x000802b_. L2TSTCLK should be pulled up for normal operation.
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
1. General Information
Page 5 of 63
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