PowerPC 750FX RISC Microprocessor
Preliminary
• L1 Cache structure
– 32K, 32-byte line, 8-way set associative
instruction cache
– 32K, 32-byte line, 8-way set associative
data cache
– Single-cycle cache access
– Pseudo-LRU replacement
– Copy-back or write-through data cache (on
a page per page basis)
– Parity on L1 tags and arrays
– 3-state (MEI) memory coherency
– Hardware support for data coherency
– Non-blocking instruction cache (one out-
standing miss)
– Non-blocking data cache (two outstanding
misses)
– No snooping of instruction cache
• Memory management unit
– 64 entry, 2-way set associative instruction
TLB (total 128)
– 64 entry, 2-way set associative data TLB
(total 128)
– Hardware reload for TLBs
– 8 instruction BATs and 8 data BATs
– Virtual memory support for up to 4 exabytes
(2
52
) virtual memory
– Real memory support for up to 4 gigabytes
(2
32
) of physical memory
– Support for big/little-endian addressing
• Dual PLLs
– Allows seamless frequency switching
• Level 2 (L2) cache
– Internal L2 cache controller and 4K-entry
tags: 512KB data SRAMs
– Two-way set-associative, supports locking
by way
– Copy-back or write-through data cache on a
page basis, or for all L2
– 64-byte sectored line size
– L2 frequency at core speed
– ECC protection on SRAM array
– Parity on L2 tags
– Supports up to 2 outstanding misses
(1 data and 1 instruction or 2 data)
• Power
– Low power consumption with low voltage
application at lower frequency
– Dynamic power management
– 3 static power save modes
(doze, nap, and sleep)
– Thermal Assist Unit (TAU)
• Bus interface
– 32-bit address bus
– 64-bit data bus (also supports 32-bit mode)
– Enhanced 60x bus: pipelines consecutive
reads to a depth of 2
– Core-to-bus frequency multipliers of 3.5x,
4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x,
8.5x, 9x, 9.5x, 10x, 11x, 12x, 13x, 14x, 15x,
16x, 17x, 18x, 19x, and 20x supported
– Supports 1.8V, 2.5V, or 3.3V I/O modes
• Reliability and serviceability
- Parity checking on 60x interface
- ECC checking on L2 cache
- Parity on the L1 arrays
- Parity on the L1 and L2 tags
• Testability
– LSSD scan design
– Powerful diagnostic and test interface
through Common On-Chip Processor
(COP) and IEEE 1149.1 (JTAG) interface
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
1. General Information
Page 4 of 63
IBM [ IBM ]
